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assembler-aarch64: Add support for emitting AES instructions #19

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assembler-aarch64: Add support for emitting AES instructions #19

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b0cd67c
assembler-aarch64: Add support for emitting AES instructions
lioncash Jan 26, 2022
59f8f49
assembler-aarch32: Add support for emitting AES instructions
lioncash Jan 26, 2022
3a52d5c
disasm-aarch32: Handle disassembly of AES instructions
lioncash Jan 26, 2022
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91 changes: 91 additions & 0 deletions src/aarch32/assembler-aarch32.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -2694,6 +2694,97 @@ bool Assembler::adr_info(Condition cond,
return false;
}

void Assembler::aesd(Condition cond, DataType dt, QRegister rd, QRegister rm) {
VIXL_ASSERT(AllowAssembler());
VIXL_ASSERT(dt.Is(Untyped8));
CheckIT(cond);

if (IsUsingT32()) {
// AESD{<c>}{<q>}.<dt> <Qd>, <Qm> ; T1
if (cond.Is(al) || AllowStronglyDiscouraged()) {
EmitT32_32(0xffb00340 | rd.Encode(22, 12) | rm.Encode(5, 0));
AdvanceIT();
return;
}
} else {
// AESD{<c>}{<q>}.<dt> <Qd>, <Qm> ; A1
if (cond.Is(al)) {
EmitA32(0xf3b00340 | rd.Encode(22, 12) | rm.Encode(5, 0));
return;
}
}
Delegate(kAesd, &Assembler::aesd, cond, dt, rd, rm);
}

void Assembler::aese(Condition cond, DataType dt, QRegister rd, QRegister rm) {
VIXL_ASSERT(AllowAssembler());
VIXL_ASSERT(dt.Is(Untyped8));
CheckIT(cond);

if (IsUsingT32()) {
// AESE{<c>}{<q>}.<dt> <Qd>, <Qm> ; T1
if (cond.Is(al) || AllowStronglyDiscouraged()) {
EmitT32_32(0xffb00300 | rd.Encode(22, 12) | rm.Encode(5, 0));
AdvanceIT();
return;
}
} else {
// AESE{<c>}{<q>}.<dt> <Qd>, <Qm> ; A1
if (cond.Is(al)) {
EmitA32(0xf3b00300 | rd.Encode(22, 12) | rm.Encode(5, 0));
return;
}
}
Delegate(kAese, &Assembler::aese, cond, dt, rd, rm);
}

void Assembler::aesimc(Condition cond,
DataType dt,
QRegister rd,
QRegister rm) {
VIXL_ASSERT(AllowAssembler());
VIXL_ASSERT(dt.Is(Untyped8));
CheckIT(cond);

if (IsUsingT32()) {
// AESIMC{<c>}{<q>}.<dt> <Qd>, <Qm> ; T1
if (cond.Is(al) || AllowStronglyDiscouraged()) {
EmitT32_32(0xffb003c0 | rd.Encode(22, 12) | rm.Encode(5, 0));
AdvanceIT();
return;
}
} else {
// AESIMC{<c>}{<q>}.<dt> <Qd>, <Qm> ; A1
if (cond.Is(al)) {
EmitA32(0xf3b003c0 | rd.Encode(22, 12) | rm.Encode(5, 0));
return;
}
}
Delegate(kAesimc, &Assembler::aesimc, cond, dt, rd, rm);
}

void Assembler::aesmc(Condition cond, DataType dt, QRegister rd, QRegister rm) {
VIXL_ASSERT(AllowAssembler());
VIXL_ASSERT(dt.Is(Untyped8));
CheckIT(cond);

if (IsUsingT32()) {
// AESMC{<c>}{<q>}.<dt> <Qd>, <Qm> ; T1
if (cond.Is(al) || AllowStronglyDiscouraged()) {
EmitT32_32(0xffb00380 | rd.Encode(22, 12) | rm.Encode(5, 0));
AdvanceIT();
return;
}
} else {
// AESMC{<c>}{<q>}.<dt> <Qd>, <Qm> ; A1
if (cond.Is(al)) {
EmitA32(0xf3b00380 | rd.Encode(22, 12) | rm.Encode(5, 0));
return;
}
}
Delegate(kAesmc, &Assembler::aesmc, cond, dt, rd, rm);
}

void Assembler::and_(Condition cond,
EncodingSize size,
Register rd,
Expand Down
26 changes: 20 additions & 6 deletions src/aarch32/assembler-aarch32.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1161,12 +1161,14 @@ class Assembler : public internal::AssemblerBase {
QRegister /*rd*/,
QRegister /*rm*/) {
USE(type);
VIXL_ASSERT((type == kVabs) || (type == kVcls) || (type == kVclz) ||
(type == kVcnt) || (type == kVneg) || (type == kVpadal) ||
(type == kVpaddl) || (type == kVqabs) || (type == kVqneg) ||
(type == kVrecpe) || (type == kVrev16) || (type == kVrev32) ||
(type == kVrev64) || (type == kVrsqrte) || (type == kVswp) ||
(type == kVtrn) || (type == kVuzp) || (type == kVzip));
VIXL_ASSERT((type == kAesd) || (type == kAese) || (type == kAesimc) ||
(type == kAesimc) || (type == kVabs) || (type == kVcls) ||
(type == kVclz) || (type == kVcnt) || (type == kVneg) ||
(type == kVpadal) || (type == kVpaddl) || (type == kVqabs) ||
(type == kVqneg) || (type == kVrecpe) || (type == kVrev16) ||
(type == kVrev32) || (type == kVrev64) || (type == kVrsqrte) ||
(type == kVswp) || (type == kVtrn) || (type == kVuzp) ||
(type == kVzip));
UnimplementedDelegate(type);
}
virtual void Delegate(InstructionType type,
Expand Down Expand Up @@ -1971,6 +1973,18 @@ class Assembler : public internal::AssemblerBase {
adr(al, size, rd, location);
}

void aesd(Condition cond, DataType dt, QRegister rd, QRegister rm);
void aesd(QRegister rd, QRegister rm) { aesd(al, Untyped8, rd, rm); }

void aese(Condition cond, DataType dt, QRegister rd, QRegister rm);
void aese(QRegister rd, QRegister rm) { aese(al, Untyped8, rd, rm); }

void aesimc(Condition cond, DataType dt, QRegister rd, QRegister rm);
void aesimc(QRegister rd, QRegister rm) { aesimc(al, Untyped8, rd, rm); }

void aesmc(Condition cond, DataType dt, QRegister rd, QRegister rm);
void aesmc(QRegister rd, QRegister rm) { aesmc(al, Untyped8, rd, rm); }

void and_(Condition cond,
EncodingSize size,
Register rd,
Expand Down
8 changes: 8 additions & 0 deletions src/aarch32/constants-aarch32.cc
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Expand Up @@ -46,6 +46,14 @@ const char* ToCString(InstructionType type) {
return "addw";
case kAdr:
return "adr";
case kAesd:
return "aesd";
case kAese:
return "aese";
case kAesimc:
return "aesimc";
case kAesmc:
return "aesmc";
case kAnd:
return "and";
case kAnds:
Expand Down
4 changes: 4 additions & 0 deletions src/aarch32/constants-aarch32.h
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Original file line number Diff line number Diff line change
Expand Up @@ -126,6 +126,10 @@ enum InstructionType {
kAdds,
kAddw,
kAdr,
kAesd,
kAese,
kAesimc,
kAesmc,
kAnd,
kAnds,
kAsr,
Expand Down
148 changes: 136 additions & 12 deletions src/aarch32/disasm-aarch32.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -1228,6 +1228,42 @@ void Disassembler::and_(Condition cond,
os() << rn << ", " << operand;
}

void Disassembler::aesd(Condition cond,
DataType dt,
QRegister rd,
QRegister rm) {
os().SetCurrentInstruction(kAesd, kNoAttribute);
os() << ToCString(kAesd) << ConditionPrinter(it_block_, cond)
<< DtPrinter(dt, Untyped8) << ' ' << rd << ", " << rm;
}

void Disassembler::aese(Condition cond,
DataType dt,
QRegister rd,
QRegister rm) {
os().SetCurrentInstruction(kAese, kNoAttribute);
os() << ToCString(kAese) << ConditionPrinter(it_block_, cond)
<< DtPrinter(dt, Untyped8) << ' ' << rd << ", " << rm;
}

void Disassembler::aesimc(Condition cond,
DataType dt,
QRegister rd,
QRegister rm) {
os().SetCurrentInstruction(kAesimc, kNoAttribute);
os() << ToCString(kAesimc) << ConditionPrinter(it_block_, cond)
<< DtPrinter(dt, Untyped8) << ' ' << rd << ", " << rm;
}

void Disassembler::aesmc(Condition cond,
DataType dt,
QRegister rd,
QRegister rm) {
os().SetCurrentInstruction(kAesmc, kNoAttribute);
os() << ToCString(kAesmc) << ConditionPrinter(it_block_, cond)
<< DtPrinter(dt, Untyped8) << ' ' << rd << ", " << rm;
}

void Disassembler::ands(Condition cond,
EncodingSize size,
Register rd,
Expand Down Expand Up @@ -26583,14 +26619,38 @@ void Disassembler::DecodeT32(uint32_t instr) {
switch (instr & 0x00000080) {
case 0x00000000: {
// 0xffb00300
UnimplementedT32_32("AESE",
instr);
unsigned rd =
ExtractQRegister(instr,
22,
12);
unsigned rm =
ExtractQRegister(instr, 5, 0);
if (((instr >> 18) & 0x3) != 0) {
UnallocatedT32(instr);
return;
}
aese(CurrentCond(),
Untyped8,
QRegister(rd),
QRegister(rm));
break;
}
case 0x00000080: {
// 0xffb00380
UnimplementedT32_32("AESMC",
instr);
unsigned rd =
ExtractQRegister(instr,
22,
12);
unsigned rm =
ExtractQRegister(instr, 5, 0);
if (((instr >> 18) & 0x3) != 0) {
UnallocatedT32(instr);
return;
}
aesmc(CurrentCond(),
Untyped8,
QRegister(rd),
QRegister(rm));
break;
}
}
Expand All @@ -26601,14 +26661,38 @@ void Disassembler::DecodeT32(uint32_t instr) {
switch (instr & 0x00000080) {
case 0x00000000: {
// 0xffb00340
UnimplementedT32_32("AESD",
instr);
unsigned rd =
ExtractQRegister(instr,
22,
12);
unsigned rm =
ExtractQRegister(instr, 5, 0);
if (((instr >> 18) & 0x3) != 0) {
UnallocatedT32(instr);
return;
}
aesd(CurrentCond(),
Untyped8,
QRegister(rd),
QRegister(rm));
break;
}
case 0x00000080: {
// 0xffb003c0
UnimplementedT32_32("AESIMC",
instr);
unsigned rd =
ExtractQRegister(instr,
22,
12);
unsigned rm =
ExtractQRegister(instr, 5, 0);
if (((instr >> 18) & 0x3) != 0) {
UnallocatedT32(instr);
return;
}
aesimc(CurrentCond(),
Untyped8,
QRegister(rd),
QRegister(rm));
break;
}
}
Expand Down Expand Up @@ -41045,12 +41129,32 @@ void Disassembler::DecodeA32(uint32_t instr) {
switch (instr & 0x00000080) {
case 0x00000000: {
// 0xf3b00300
UnimplementedA32("AESE", instr);
unsigned rd =
ExtractQRegister(instr, 22, 12);
unsigned rm = ExtractQRegister(instr, 5, 0);
if (((instr >> 18) & 0x3) != 0) {
UnallocatedA32(instr);
return;
}
aese(CurrentCond(),
Untyped8,
QRegister(rd),
QRegister(rm));
break;
}
case 0x00000080: {
// 0xf3b00380
UnimplementedA32("AESMC", instr);
unsigned rd =
ExtractQRegister(instr, 22, 12);
unsigned rm = ExtractQRegister(instr, 5, 0);
if (((instr >> 18) & 0x3) != 0) {
UnallocatedA32(instr);
return;
}
aesmc(CurrentCond(),
Untyped8,
QRegister(rd),
QRegister(rm));
break;
}
}
Expand All @@ -41061,12 +41165,32 @@ void Disassembler::DecodeA32(uint32_t instr) {
switch (instr & 0x00000080) {
case 0x00000000: {
// 0xf3b00340
UnimplementedA32("AESD", instr);
unsigned rd =
ExtractQRegister(instr, 22, 12);
unsigned rm = ExtractQRegister(instr, 5, 0);
if (((instr >> 18) & 0x3) != 0) {
UnallocatedA32(instr);
return;
}
aesd(CurrentCond(),
Untyped8,
QRegister(rd),
QRegister(rm));
break;
}
case 0x00000080: {
// 0xf3b003c0
UnimplementedA32("AESIMC", instr);
unsigned rd =
ExtractQRegister(instr, 22, 12);
unsigned rm = ExtractQRegister(instr, 5, 0);
if (((instr >> 18) & 0x3) != 0) {
UnallocatedA32(instr);
return;
}
aesimc(CurrentCond(),
Untyped8,
QRegister(rd),
QRegister(rm));
break;
}
}
Expand Down
8 changes: 8 additions & 0 deletions src/aarch32/disasm-aarch32.h
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Original file line number Diff line number Diff line change
Expand Up @@ -639,6 +639,14 @@ class Disassembler {

void adr(Condition cond, EncodingSize size, Register rd, Location* location);

void aesd(Condition cond, DataType dt, QRegister rd, QRegister rm);

void aese(Condition cond, DataType dt, QRegister rd, QRegister rm);

void aesimc(Condition cond, DataType dt, QRegister rd, QRegister rm);

void aesmc(Condition cond, DataType dt, QRegister rd, QRegister rm);

void and_(Condition cond,
EncodingSize size,
Register rd,
Expand Down
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