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hw-mgmt: patches: Change dpu attribute permission
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This patch gives read permission for dpu[1-4]_pwr,
dpu[1-4]_pwr, dpu[1-4]_rst attributes.

Bugs #4023734

Signed-off-by: Ciju Rajan K <[email protected]>
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@ciju-nvidia
ciju-nvidia committed Oct 28, 2024
1 parent 1486875 commit 8c0e4c9
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Showing 2 changed files with 24 additions and 24 deletions.
24 changes: 12 additions & 12 deletions ...s-kernel/linux/linux-5.10/0299-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch
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Original file line number Diff line number Diff line change
Expand Up @@ -507,50 +507,50 @@ index 785f5870d..e3cef3c6d 100644
+ .label = "dpu1_rst",
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(0),
+ .mode = 0200,
+ .mode = 0644,
},
{
- .label = "tacho10",
+ .label = "dpu2_rst",
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(1),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "dpu3_rst",
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(2),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "dpu4_rst",
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(3),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "dpu1_pwr",
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(0),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "dpu2_pwr",
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(1),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "dpu3_pwr",
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(2),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "dpu4_pwr",
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(3),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "reset_long_pb",
Expand Down Expand Up @@ -800,25 +800,25 @@ index 785f5870d..e3cef3c6d 100644
+ .label = "dpu1_pwr_force",
+ .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(0),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "dpu2_pwr_force",
+ .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(1),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "dpu3_pwr_force",
+ .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(2),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "dpu4_pwr_force",
+ .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(3),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "ufm_done",
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24 changes: 12 additions & 12 deletions ...es-kernel/linux/linux-6.1/0092-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch
View file
Original file line number Diff line number Diff line change
Expand Up @@ -507,50 +507,50 @@ index cafa4f762..0949f32ad 100644
+ .label = "dpu1_rst",
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(0),
+ .mode = 0200,
+ .mode = 0644,
},
{
- .label = "tacho10",
+ .label = "dpu2_rst",
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(1),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "dpu3_rst",
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(2),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "dpu4_rst",
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(3),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "dpu1_pwr",
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(0),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "dpu2_pwr",
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(1),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "dpu3_pwr",
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(2),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "dpu4_pwr",
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(3),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "reset_long_pb",
Expand Down Expand Up @@ -800,25 +800,25 @@ index cafa4f762..0949f32ad 100644
+ .label = "dpu1_pwr_force",
+ .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(0),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "dpu2_pwr_force",
+ .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(1),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "dpu3_pwr_force",
+ .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(2),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "dpu4_pwr_force",
+ .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(3),
+ .mode = 0200,
+ .mode = 0644,
+ },
+ {
+ .label = "ufm_done",
Expand Down

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