Skip to content
View MikeOpenHWGroup's full-sized avatar
💭
Making CORE-V safe for the world to use.
💭
Making CORE-V safe for the world to use.

Organizations

@openhwgroup

Block or report MikeOpenHWGroup

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. riscv-dv riscv-dv Public

    Forked from chipsalliance/riscv-dv

    SV/UVM based instruction generator for RISC-V processor verification

    SystemVerilog 1 1

  2. openhwgroup/cv32e40p openhwgroup/cv32e40p Public

    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

    SystemVerilog 960 419

  3. openhwgroup/core-v-verif openhwgroup/core-v-verif Public

    Functional verification project for the CORE-V family of RISC-V cores.

    Assembly 444 221

  4. openhwgroup/programs openhwgroup/programs Public

    Documentation for the OpenHW Group's set of CORE-V RISC-V cores

    HTML 195 96