I2C-in-verilog

Verilog Code for I2C Protocol

I2C Controller Module

An I2C (Inter-Integrated Circuit) controller module implemented in Verilog for facilitating communication between a master device and slave devices using the I2C protocol. This project is designed to handle basic I2C operations, such as sending a slave address, transmitting data, and receiving acknowledgment.

Features

• Slave Address Transmission: Transmits a 7-bit slave address to initiate communication.
• Acknowledgment Handling: Detects acknowledgment (ACK) or no-acknowledgment (NACK) signals from the slave device.
• Clock Generation: Includes an SCL clock generator with configurable frequency.
• Data Transmission: Supports writing an 8-bit data word to the slave device.
• Customizable Parameters: Configurable slave address and data.

Code Structure

The Verilog module consists of the following components:

1. Clock Divider: Generates the SCL signal from the input clock.
2. State Machine: Controls the flow of operations based on the I2C protocol.
3. SDA Control: Manages the bidirectional data line (SDA) based on the current state.
4. Acknowledgment Management: Detects and handles ACK or NACK signals.

How It Works

State Machine

The controller operates using a finite state machine (FSM) with the following states:

1. IDLE: Initial state where the controller waits for a start condition.
2. START: Generates a start condition on the SDA line.
3. SEND_SLAVE_ADDR: Transmits the 7-bit slave address.
4. ACK_WAIT: Waits for an acknowledgment signal from the slave.
5. SEND_RW_BIT: Sends the read/write bit.
6. SEND_DATA: Transmits the 8-bit data to the slave.
7. DATA_ACK_WAIT: Waits for acknowledgment after data transmission.
8. STOP: Generates a stop condition on the SDA line.
9. DONE: Returns to the IDLE state after completing the operation.

Signals

• SCL: Clock signal generated by the controller.
• SDA: Bidirectional data line.
• ack_ready: Ensures acknowledgment handling begins after the slave address is fully transmitted.

Usage

Parameters

• SLAVE_ADDR: Specify the 7-bit address of the slave device (default: 7'h13).
• DATA: Specify the 8-bit data to be written (default: 8'b10001000).

Inputs

• clk: Input clock signal (e.g., 100 kHz).
• rst: Reset signal to initialize the controller.

Outputs

• scl: Clock line for the I2C communication.

Bidirectional

• sda: Data line for the I2C communication.

Simulation

Run a testbench to simulate the behavior of the I2C controller. Ensure the following:

1. The SDA line transmits the correct slave address.
2. The acknowledgment is detected accurately.
3. The STOP condition is generated after the transaction.
4. Make sure to run the simulation for at least 5us.

Example Simulation Output

SCL: 1, State: 0, SDA: 1
SCL: 0, State: 0, SDA: 1
SCL: 1, State: 1, SDA: 0
SCL: 0, State: 1, SDA: 0
SCL: 1, State: 2, SDA: 0
SCL: 0, State: 2, SDA: 0
SCL: 1, State: 2, SDA: 1
ACK_WAIT: Time=1815000ns, SCL=1, SDA=1, ACK_Received=0
SCL: 1, State: 3, SDA: 1
SCL: 0, State: 3, SDA: 0