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Fixes for wire management in Catalyst #784
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No new assumptions are made, but implicit assumptions are made more explicit.
Codecov ReportAll modified and coverable lines are covered by tests ✅
Additional details and impacted files@@ Coverage Diff @@
## main #784 +/- ##
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Coverage 98.08% 98.09%
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Files 70 70
Lines 9731 9740 +9
Branches 780 782 +2
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+ Hits 9545 9554 +9
Misses 151 151
Partials 35 35 ☔ View full report in Codecov by Sentry. |
@dime10 This does, in fact, allow allocating 0 qubits (at least trivally) and provides a helpful error message when wire count is too low the requested circuit. Thank you! LGTM! (With that said, the issue about suspicious "extra" phase gates in |
Thank you! I will have another look at the original issue then :) |
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Do you know why it fails on kokkos?
Hmm, will need to investigate :/ |
@dime10 it is an issue with kokkos:
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And it only happens with 0 qubits. Could be an upstream issue then, while |
@erick-xanadu I've disabled those tests on kokkos, don't think it's particularly important that they run on all devices. It's mainly to see that Catalyst allows 0 qubits end to end. |
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Just that minor comment.
This PR contains several improvements regarding the wire handling in Catalyst:
wires
property of devicesRelated GitHub Issues: #780
[sc-65105]