[FPGA] Some latch fixes #75

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Run time

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Job	Run time
check-license	16s
tc-gcc	42m 59s
check-trailing-whitespaces	11s
tc-isa-sim	9m 21s
tc-verilator	6m 3s
tc-llvm	1h 27m 55s
compile-ara (2_lanes)	2m 42s
compile-ara (4_lanes)	4m 0s
compile-ara (8_lanes)	3m 53s
compile-ara (16_lanes)	4m 22s
check-clang-format	58s
compile-riscv-tests (2_lanes)	9m 26s
compile-apps (2_lanes)	46s
compile-riscv-tests (4_lanes)	3m 20s
compile-apps (4_lanes)	44s
compile-riscv-tests (8_lanes)	4m 49s
compile-riscv-tests (16_lanes)	3m 16s
compile-apps (8_lanes)	45s
compile-apps (16_lanes)	50s
simulate	0s
benchmark	0s
roofline	0s
riscv-tests-spike	1m 33s
riscv-tests-simv (2_lanes)	2m 26s
riscv-tests-simv (4_lanes)	2m 5s
riscv-tests-simv (8_lanes)	2m 7s
riscv-tests-simv (16_lanes)	2m 30s
clean-up	5s
clean-up-compile-runs (2_lanes)	5s
clean-up-compile-runs (4_lanes)	5s
clean-up-compile-runs (8_lanes)	4s
clean-up-compile-runs (16_lanes)	4s
	3h 17m 40s