[FPGA] Synthesis and latch fixes

PolyMTL-Gr2m · Nov 14, 2023 · 575fa15 · 575fa15
1 parent 7358592
commit 575fa15
Show file tree

Hide file tree

Showing 5 changed files with 15 additions and 8 deletions.
diff --git a/hardware/src/ara_soc.sv b/hardware/src/ara_soc.sv
@@ -232,7 +232,7 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #(
   );
 
 `ifndef SPYGLASS
-  tc_sram #(
+  tc_sram_wrapper #(
     .NumWords (L2NumWords  ),
     .NumPorts (1           ),
     .DataWidth(AxiDataWidth),

diff --git a/hardware/src/lane/simd_mul.sv b/hardware/src/lane/simd_mul.sv
@@ -164,7 +164,7 @@ module simd_mul import ara_pkg::*; import rvv_pkg::*; #(
     always_comb begin : p_mul
       // Default assignment
       result_o = '0;
-
+      r = '0;
       unique case (op)
         // Single-Width integer multiply instructions
         VMUL: for (int l = 0; l < 1; l++) result_o[64*l +: 64] = mul_res.w128[l][63:0];
@@ -204,6 +204,7 @@ module simd_mul import ara_pkg::*; import rvv_pkg::*; #(
     end: gen_mul
 
     always_comb begin : p_mul
+      r = '0;
       unique case (op)
         // Single-Width integer multiply instructions
         VMUL: for (int l = 0; l < 2; l++) result_o[32*l +: 32] = mul_res.w64[l][31:0];
@@ -278,6 +279,7 @@ module simd_mul import ara_pkg::*; import rvv_pkg::*; #(
     end : gen_mul
 
     always_comb begin : p_mul
+      r = '0;
       unique case (op)
         // Single-Width integer multiply instructions
         VMUL: for (int l = 0; l < 8; l++) result_o[8*l +: 8] = mul_res.w16[l][7:0];

diff --git a/hardware/src/lane/vector_regfile.sv b/hardware/src/lane/vector_regfile.sv
@@ -79,7 +79,7 @@ module vector_regfile import ara_pkg::*; #(
     assign vrf_clk = clk_i;
 `endif
 
-    tc_sram #(
+    tc_sram_wrapper #(
       .NumWords (NumWords ),
       .DataWidth(DataWidth),
       .NumPorts (1        )

diff --git a/openpiton/axi_noc_bridge.sv b/openpiton/axi_noc_bridge.sv
@@ -804,7 +804,7 @@ begin
 end 
 
 
-always_ff@(posedge clk or negedge rst_n)
+always_comb //@(posedge clk or negedge rst_n)
 begin
     flit_state_next = flit_state_f;
     unique case (flit_state_f)
@@ -1010,6 +1010,9 @@ begin
                 `endif 
                     flit_ready = 1'b1;
                 end
+                default: begin
+                    flit_ready = 1'b0;
+                end
             endcase
         end
 

diff --git a/openpiton/noc_response_axi.sv b/openpiton/noc_response_axi.sv
@@ -44,7 +44,7 @@ always_comb begin
 end 
 
 endmodule 
-module noc_response_axi #(
+module noc_response_axi import wt_cache_pkg::*; #(
     parameter AXI_DATA_WIDTH  = 64,
   `ifndef ARA_REQ2MEM
     parameter MSG_TYPE_INVAL       = 2'd0, // Invalid Message
@@ -84,7 +84,7 @@ module noc_response_axi #(
 
 localparam LAST_TRANSFER_FLAG_WIDTH = 1; 
 
-typedef enum logic [2:0] {
+typedef enum logic [1:0] {
     NOC_IN_STATE_HEADER          = 2'b00, // Header 0
     NOC_IN_STATE_READ_DATA       = 2'b01, // Data Lines
     NOC_IN_STATE_STORE_ACK       = 2'b10  // for the fifo read when store happens
@@ -194,7 +194,8 @@ end
 
 if (AXI_DATA_WIDTH == 64) begin 
     always_comb begin 
-        rdata_fifo_wdata = {valid_last_read_transfer, {<<8{noc_data_in}}};
+        //rdata_fifo_wdata = {valid_last_read_transfer, {<<8{noc_data_in}}};
+        rdata_fifo_wdata = {valid_last_read_transfer, swendian64(noc_data_in)};
 
         rdata_fifo_wval = read_size ? (noc_in_count_f >= 0) && (noc_in_state_f == NOC_IN_STATE_READ_DATA) && noc_io_go : 
                             read_word_select ? (noc_in_count_f == 1) && (noc_in_state_f == NOC_IN_STATE_READ_DATA) && noc_io_go :
@@ -209,7 +210,8 @@ else begin
         else first_word <= first_word; 
     end 
     always_comb begin 
-        rdata_fifo_wdata = {valid_last_read_transfer, {<<8{first_word, noc_data_in}}};
+        //rdata_fifo_wdata = {valid_last_read_transfer, {<<8{first_word, noc_data_in}}};
+        rdata_fifo_wdata = {valid_last_read_transfer, swendian64({first_word, noc_data_in})};
 
         rdata_fifo_wval = (noc_in_count_f == 1) && (noc_in_state_f == NOC_IN_STATE_READ_DATA) && noc_io_go;
     end