[FPGA] Fix latch in simd_mul

PolyMTL-Gr2m · Apr 26, 2024 · 62e2832 · 62e2832
1 parent 9fc3680
commit 62e2832
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/hardware/src/lane/simd_mul.sv b/hardware/src/lane/simd_mul.sv
@@ -242,6 +242,7 @@ module simd_mul import ara_pkg::*; import rvv_pkg::*; #(
     end : gen_mul
 
     always_comb begin : p_mul
+      r = '0;
       unique case (op)
         // Single-Width integer multiply instructions
         VMUL: for (int l = 0; l < 4; l++) result_o[16*l +: 16] = mul_res.w32[l][15:0];