[Polara] Bug fix, CVA6 mem interface fixed, adding CVA6 configs

PolyMTL-Gr2m · Aug 4, 2023 · 761b4bf · 761b4bf
1 parent 37de0a7
commit 761b4bf
Showing 1 changed file with 14 additions and 26 deletions.
diff --git a/openpiton/ara_verilog_wrap.sv b/openpiton/ara_verilog_wrap.sv
@@ -189,15 +189,7 @@ module ara_verilog_wrap
 
     // Accelerator ports
     accelerator_req_t                     acc_req;
-    logic                                 acc_req_valid;
-    logic                                 acc_req_ready;
     accelerator_resp_t                    acc_resp;
-    logic                                 acc_resp_valid;
-    logic                                 acc_resp_ready;
-    logic                                 acc_cons_en; // unused
-    logic              [AxiAddrWidth-1:0] inval_addr;
-    logic                                 inval_valid;
-    logic                                 inval_ready;
 
 
     /////////////////////////////
@@ -316,12 +308,20 @@ module ara_verilog_wrap
       NrPMPEntries:          NrPMPEntries
     };
 
-
-
-
+  localparam ariane_pkg::cva6_cfg_t CVA6Cfg = {
+      unsigned'(2                                       ),  // NrCommitPorts
+      unsigned'(0                                       ),  // IsRVFI
+      unsigned'(AxiAddrWidth                            ),  // AxiAddrWidth
+      unsigned'(AxiNarrowDataWidth                      ),  // AxiDataWidth
+      unsigned'(AxiIdWidth                              ),  // AxiIdWidth
+      unsigned'(AxiUserWidth                            )   // AxiUserWidth
+  };
 
   ariane #(
-    .ArianeCfg     (ArianeOpenPitonCfg         )
+    .CVA6Cfg          (CVA6Cfg               ),
+    .ArianeCfg        (ArianeOpenPitonCfg    ),
+    .noc_req_t        ( wt_cache_pkg::l15_req_t ),
+    .noc_resp_t       ( wt_cache_pkg::l15_rtrn_t )
   ) ariane (
     .clk_i            (clk_i                 ),
     .rst_ni           (spc_grst_l            ),
@@ -331,15 +331,8 @@ module ara_verilog_wrap
     .ipi_i            (ipi                   ),
     .time_irq_i       (time_irq              ),
     .debug_req_i      (debug_req             ),
-    // Accelerator ports
-`ifdef PITON_ARIANE
-    .l15_req_o        (l15_req               ),
-    .l15_rtrn_i       (l15_rtrn              )
-`else
-    // Memory interface
-    .axi_req_o        (ariane_narrow_axi_req ),
-    .axi_resp_i       (ariane_narrow_axi_resp)
-`endif
+    .noc_req_o        (l15_req               ),
+    .noc_resp_i       (l15_rtrn              )
   );
 
   logic  scan_enable_i;
@@ -377,11 +370,6 @@ module ara_verilog_wrap
   soc_narrow_req_t  periph_cut_narrow_axi_req;
   soc_narrow_resp_t periph_cut_narrow_axi_resp;
 
-
-  /////////////////////////
-  //  NOC Bridge         //
-  /////////////////////////
-
   /////////////////////////
   //  NOC Bridge         //
   /////////////////////////