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Small modifications for ASIC synthesis
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Yoan Fournier committed Oct 10, 2023
1 parent d864895 commit c26048b
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Showing 3 changed files with 6 additions and 11 deletions.
2 changes: 1 addition & 1 deletion openpiton/ara_verilog_wrap.sv
Original file line number Diff line number Diff line change
Expand Up @@ -98,7 +98,7 @@ module ara_verilog_wrap
// L15 (memory side)
// output [$size(wt_cache_pkg::l15_req_t)-1:0] l15_req_o,
// input [$size(wt_cache_pkg::l15_rtrn_t)-1:0] l15_rtrn_i
output wt_cache_pkg::l15_rtrn_t l15_req_o,
output wt_cache_pkg::l15_req_t l15_req_o,
input wt_cache_pkg::l15_rtrn_t l15_rtrn_i
`else
// AXI (memory side)
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11 changes: 4 additions & 7 deletions openpiton/axi_noc_bridge.sv
Original file line number Diff line number Diff line change
Expand Up @@ -514,7 +514,7 @@ end

/**fifo for wsize**/
sync_fifo #(
.DSIZE(8),
.DSIZE(3),
.ASIZE(5),
.MEMSIZE(16) // should be 2 ^ (ASIZE-1)
) awsize_fifo (
Expand Down Expand Up @@ -634,7 +634,7 @@ end

/** fifo for read len***/
sync_fifo #(
.DSIZE(8),
.DSIZE(3),
.ASIZE(5),
.MEMSIZE(16) // should be 2 ^ (ASIZE-1)
) arsize_fifo (
Expand Down Expand Up @@ -804,7 +804,8 @@ begin
end


always_ff@(posedge clk or negedge rst_n)
//always_ff@(posedge clk or negedge rst_n)
always_comb
begin
flit_state_next = flit_state_f;
unique case (flit_state_f)
Expand Down Expand Up @@ -1035,8 +1036,4 @@ end
assign noc_valid_out = flit_ready;
assign noc_data_out = flit;

<<<<<<< HEAD
endmodule
=======
endmodule
>>>>>>> 37de0a75fe97ef8f4d13821dc23ae26797435baa
4 changes: 1 addition & 3 deletions openpiton/axilite_noc_bridge.sv
Original file line number Diff line number Diff line change
Expand Up @@ -472,7 +472,7 @@ assign fifo_has_packet = (type_fifo_out == MSG_TYPE_STORE) ? (!awaddr_fifo_empty
// assign noc_load_done = noc_last_data && type_fifo_out == MSG_TYPE_LOAD; // We need to file 2 meaningless data flit (16 bytes) for swap_wb load
`endif

generate begin

genvar k;
if (AXI_LITE_DATA_WIDTH < MIN_NOC_DATA_WIDTH) begin
for (k=0; k< MIN_NOC_DATA_WIDTH/AXI_LITE_DATA_WIDTH; k = k + 1)
Expand All @@ -486,8 +486,6 @@ generate begin
assign out_data[k] = wdata_fifo_out[(k+1)*MIN_NOC_DATA_WIDTH-1 : k*MIN_NOC_DATA_WIDTH];
end
end
end
endgenerate



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