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Strongly rewritten/reordered#3

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rodrigomelo9 wants to merge 23 commits intomainPyFPGA/poc:mainfrom rewritePyFPGA/poc:rewriteCopy head branch name to clipboard

+322-240

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Commits on Nov 26, 2021

• Added the hdl directory with VHDL files

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• vivado: rewritten (vlog.tcl is WIP)

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• hdl: added Verilog files (WIP)

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• vivado: finished vlog.tcl

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• resources: submodule updated

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• hdl: removed (content already in the 'resources' submodule)

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• ghdl: added a VHDL example

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Commits on Nov 28, 2021

• resources: submodule updated

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• ghdl: added the check of a CHARACTER generic and a README.md file with notes

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• vivado: added the check of a CHARACTER generic and a README.md file with notes

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• resources: submodule updated

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• yosys: added a Verilog example

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• vivado: fixed Verilog example after changes into resources

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• ghdl: updated README.md

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Commits on Nov 29, 2021

• Added clean.sh

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• openflow: removed ghdl.sh and yosys.sh

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• yosys: added vhdl.sh

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• openflow: flow.sh was split into yosys/icestorm and yosys/trellis

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Commits on Nov 30, 2021

• ghdl: updated the employed Docker container

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• yosys: updated the employed Docker container

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Commits on Dec 12, 2021

• ghdl: added a more concise alternative

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• ghdl-yosys: added

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Commits on May 15, 2022

• resources: submodule updated

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