2.3.1

Scheduler lock only when current priority lower than ceiling

README.md

@@ -47,7 +47,20 @@ The preemptive SST and non-preemptive SST0 implement actually *the same*
 [SST API](https://github.com/QuantumLeaps/Super-Simple-Tasker/tree/main/include)
 (either in C or C++).
 
-## Hardware RTOS for ARM Cortex-M
+
+## Related Approaches
+The SST RTOS kernel is related to, although *not* based on, the following
+approaches:
+
+- [Operating System - OSEK VDX](https://www.osek-vdx.org/mirror/os21r1.pdf)
+- [A Stack-Based Resource Allocation Policy for Realtime Processes](https://ieeexplore.ieee.org/document/128747)
+- [Real-Time For the Masses](https://www.diva-portal.org/smash/get/diva2:1005680/FULLTEXT01.pdf)
+- [crect: A C++, compile-time, reactive RTOS](https://github.com/korken89/crect)
+- [Rust's Real Time For the Masses (RTFM)](https://lonesometraveler.github.io/2020/05/22/RTFM.html)
+- [Real-Time Interrupt-driven Concurrency (RTIC)](https://rtic.rs/1/book/en)
+
+
+# Hardware RTOS for ARM Cortex-M
 [SST for ARM Cortex-M](sst_c/ports/arm-cm) provides a unique
 **hardware implementation** of the SST API for ARM Cortex-M (M0, M0+, M3,
 M4, M7, M23, M33). The SST "hardware RTOS" for ARM Cortex-M is fully
@@ -60,7 +73,6 @@ compatible with the requirements of
 The SST hardware implementation is likely the most performant and efficient
 **hard-real time RTOS** kernel for ARM Cortex-M.
 
-
 # SST Videos
 SST has been presented at the Embedded Online Conference 2023 and the videos
 are available on YouTube:
@@ -188,18 +200,6 @@ intended to remain the home of SST. To contribute, please clone, fork,
 and submit **pull requests** to incorporate your changes.
 
 
-# Related Approaches
-The SST RTOS kernel is related to, although *not* based on, the following
-approaches:
-
-- [Operating System - OSEK VDX](https://www.osek-vdx.org/mirror/os21r1.pdf)
-- [A Stack-Based Resource Allocation Policy for Realtime Processes](https://ieeexplore.ieee.org/document/128747)
-- [Real-Time For the Masses](https://www.diva-portal.org/smash/get/diva2:1005680/FULLTEXT01.pdf)
-- [Rust's Real Time For the Masses (RTFM)](https://lonesometraveler.github.io/2020/05/22/RTFM.html)
-- [crect: A C++, compile-time, reactive RTOS](https://github.com/korken89/crect)
-- [Real-Time Interrupt-driven Concurrency (RTIC)](https://rtic.rs/1/book/en)
-
-
 # How to Help this Project?
 If you like this project, please **spread the word** about SST on various
 forums, social media, and other venues frequented by embedded folks!

sst_c/ports/arm-cm/sst_port.c

@@ -23,7 +23,7 @@
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 ===========================================================================*/
-#include "sst.h"     /* Super-Simple Tasker (SST/C) */
+#include "sst.h"        /* Super-Simple Tasker (SST/C) */
 #include "dbc_assert.h" /* Design By Contract (DBC) assertions */
 
 DBC_MODULE_NAME("sst_port") /* for DBC assertions in this module */
@@ -146,14 +146,14 @@ void SST_Task_setIRQ(SST_Task * const me, uint8_t irq) {
 SST_LockKey SST_Task_lock(SST_TaskPrio ceiling) {
 #if (__ARM_ARCH == 6) /* ARMv6-M? */
     /* NOTE:
-    * ARMv6-M (Cortex-M0/M0+/M1) do NOT support the BASEPRI register.
+    * ARMv6-M (Cortex-M0/M0+/M1) do NOT support the BASEPRI register
     * and simple selective scheduler locking is not possible.
-    * Instead, on this architectures, SST scheduler lock is implemented
-    * by temporarily raising the current task priority to the ceiling
-    * level.
+    * Instead, on this architectures, SST scheduler lock can be
+    * implemented by temporarily raising the current task priority
+    * to the ceiling level.
     */
     /* TBD... */
-    (void)ceiling; /* unused param */
+    (void)ceiling; /* unused param for now */
     return 0U;
 #else  /* ARMv7-M+ */
     /* NOTE:
@@ -164,15 +164,21 @@ SST_LockKey SST_Task_lock(SST_TaskPrio ceiling) {
                          << nvic_prio_shift;
     SST_LockKey basepri_;
     __asm volatile ("mrs %0,BASEPRI" : "=r" (basepri_) :: );
-    __asm volatile ("cpsid i\n msr BASEPRI,%0\n cpsie i"
-                    :: "r" (nvic_prio) : );
+    if (basepri_ > nvic_prio) { /* current priority lower than the ceiling? */
+        __asm volatile ("cpsid i\n msr BASEPRI,%0\n cpsie i"
+                        :: "r" (nvic_prio) : );
+    }
+    else {
+        basepri_ = nvic_prio;
+    }
     return basepri_;
 #endif
 }
 /*..........................................................................*/
 void SST_Task_unlock(SST_LockKey lock_key) {
 #if (__ARM_ARCH == 6) /* ARMv6-M? */
     /* TBD... */
+    (void)lock_key; /* unused param for now */
 #else  /* ARMv7-M+ */
     /* NOTE:
     * ARMv7-M+ support the BASEPRI register and the selective SST scheduler

sst_cpp/ports/arm-cm/sst_port.cpp

@@ -149,14 +149,14 @@ void Task::setIRQ(std::uint32_t irq) noexcept {
 LockKey Task::lock(TaskPrio ceiling) {
 #if (__ARM_ARCH == 6) // ARMv6-M?
     // NOTE:
-    // ARMv6-M (Cortex-M0/M0+/M1) do NOT support the BASEPRI register.
+    // ARMv6-M (Cortex-M0/M0+/M1) do NOT support the BASEPRI register
     // and simple selective scheduler locking is not possible.
-    // Instead, on this architectures, SST scheduler lock is implemented
-    // by temporarily raising the current task priority to the ceiling
-    // level.
+    // Instead, on this architectures, SST scheduler lock can be
+    // implemented by temporarily raising the current task priority
+    // to the ceiling level.
     //
     /// TBD...
-    static_cast<void>(ceiling); // unused param
+    static_cast<void>(ceiling); // unused param for now
     return 0U;
 #else  // ARMv7-M+
     // NOTE:
@@ -167,15 +167,21 @@ LockKey Task::lock(TaskPrio ceiling) {
                          << nvic_prio_shift;
     LockKey basepri_;
     __asm volatile ("mrs %0,BASEPRI" : "=r" (basepri_) :: );
-    __asm volatile ("cpsid i\n msr BASEPRI,%0\n cpsie i"
-                    :: "r" (nvic_prio) : );
+    if (basepri_ > nvic_prio) { // current priority lower than the ceiling?
+        __asm volatile ("cpsid i\n msr BASEPRI,%0\n cpsie i"
+                        :: "r" (nvic_prio) : );
+    }
+    else {
+        basepri_ = nvic_prio;
+    }
     return basepri_;
 #endif
 }
 //............................................................................
 void Task::unlock(LockKey lock_key) {
 #if (__ARM_ARCH == 6) // ARMv6-M?
     // TBD...
+    static_cast<void>(lock_key); // unused param for now
 #else  // ARMv7-M+
     // NOTE:
     // ARMv7-M+ support the BASEPRI register and the selective SST scheduler