Updated tests to use the now class style iforms in isa_data

osaca/db_interface.py

@@ -10,6 +10,10 @@
 import ruamel.yaml
 
 from osaca.semantics import MachineModel
+from osaca.parser import InstructionForm
+from osaca.parser.memory import MemoryOperand
+from osaca.parser.register import RegisterOperand
+from osaca.parser.immediate import ImmediateOperand
 
 
 def sanity_check(arch: str, verbose=False, internet_check=False, output_file=sys.stdout):
@@ -432,18 +436,20 @@ def _check_sanity_arch_db(arch_mm, isa_mm, internet_check=True):
 
         # Check operands
         for operand in instr_form["operands"]:
-            if operand["class"] == "register" and not ("name" in operand or "prefix" in operand):
+            if isinstance(operand, RegisterOperand) and not (
+                operand.name != None or operand.prefix != None
+            ):
                 # Missing 'name' key
                 bad_operand.append(instr_form)
-            elif operand["class"] == "memory" and (
-                "base" not in operand
-                or "offset" not in operand
-                or "index" not in operand
-                or "scale" not in operand
+            elif isinstance(operand, MemoryOperand) and (
+                operand.base is None
+                or operand.offset is None
+                or operand.index is None
+                or operand.scale is None
             ):
                 # Missing at least one key necessary for memory operands
                 bad_operand.append(instr_form)
-            elif operand["class"] == "immediate" and "imd" not in operand:
+            elif isinstance(operand, ImmediateOperand) and operand.imd == None:
                 # Missing 'imd' key
                 bad_operand.append(instr_form)
     # every entry exists twice --> uniquify
@@ -602,15 +608,19 @@ def _get_sanity_report_verbose(
 
 
 def _get_full_instruction_name(instruction_form):
-    """Get full instruction form name/identifier string out of given instruction form."""
+    """Get one instruction name string including the mnemonic and all operands."""
     operands = []
     for op in instruction_form["operands"]:
-        op_attrs = [
-            y + ":" + str(op[y])
-            for y in list(filter(lambda x: True if x != "class" else False, op))
-        ]
-        operands.append("{}({})".format(op["class"], ",".join(op_attrs)))
-    return "{}  {}".format(instruction_form["name"], ",".join(operands))
+        if isinstance(op, RegisterOperand):
+            op_attrs = []
+            if op.name != None:
+                op_attrs.append("name:" + op.name)
+            if op.prefix != None:
+                op_attrs.append("prefix:" + op.prefix)
+            if op.shape != None:
+                op_attrs.append("shape:" + op.shape)
+            operands.append("{}({})".format("register", ",".join(op_attrs)))
+    return "{}  {}".format(instruction_form["name"].lower(), ",".join(operands))
 
 
 def __represent_none(self, data):

osaca/frontend.py

@@ -237,7 +237,7 @@ def full_analysis_dict(
         if lcd_warning:
             warnings.append("LCDWarning")
 
-        #if INSTR_FLAGS.TP_UNKWN in [flag for instr in kernel for flag in instr.flags]:
+        # if INSTR_FLAGS.TP_UNKWN in [flag for instr in kernel for flag in instr.flags]:
         #    warnings.append("UnknownInstrWarning")
 
         tp_sum = ArchSemantics.get_throughput_sum(kernel) or kernel[0].port_pressure

osaca/semantics/arch_semantics.py

@@ -257,7 +257,7 @@ def assign_tp_lt(self, instruction_form):
                     if instruction_data_reg:
                         assign_unknown = False
                         reg_type = self._parser.get_reg_type(
-                            instruction_data_reg["operands"][
+                            instruction_data_reg.operands[
                                 operands.index(self._create_reg_wildcard())
                             ]
                         )
@@ -318,10 +318,9 @@ def assign_tp_lt(self, instruction_form):
                                 not in instruction_form.semantic_operands["destination"]
                                 and all(
                                     [
-                                        "post_indexed" in op["memory"]
-                                        or "pre_indexed" in op["memory"]
+                                        op.post_indexed or op.pre_indexed
                                         for op in instruction_form.semantic_operands["src_dst"]
-                                        if "memory" in op
+                                        if isinstance(op, MemoryOperand)
                                     ]
                                 )
                             ):
@@ -343,10 +342,8 @@ def assign_tp_lt(self, instruction_form):
                                 sum(x) for x in zip(data_port_pressure, st_data_port_pressure)
                             ]
                             data_port_uops += st_data_port_uops
-                        throughput = max(
-                            max(data_port_pressure), instruction_data_reg["throughput"]
-                        )
-                        latency = instruction_data_reg["latency"]
+                        throughput = max(max(data_port_pressure), instruction_data_reg.throughput)
+                        latency = instruction_data_reg.latency
                         # Add LD and ST latency
                         latency += (
                             self._machine_model.get_load_latency(reg_type)
@@ -358,7 +355,7 @@ def assign_tp_lt(self, instruction_form):
                             if INSTR_FLAGS.HAS_ST in instruction_form.flags
                             else 0
                         )
-                        latency_wo_load = instruction_data_reg["latency"]
+                        latency_wo_load = instruction_data_reg.latency
                         # add latency of ADD if post- or pre-indexed load
                         # TODO more investigation: check dot-graph, wrong latency distribution!
                         # if (
@@ -379,12 +376,12 @@ def assign_tp_lt(self, instruction_form):
                             for x in zip(
                                 data_port_pressure,
                                 self._machine_model.average_port_pressure(
-                                    instruction_data_reg["port_pressure"]
+                                    instruction_data_reg.port_pressure
                                 ),
                             )
                         ]
                         instruction_form.port_uops = list(
-                            chain(instruction_data_reg["port_pressure"], data_port_uops)
+                            chain(instruction_data_reg.port_pressure, data_port_uops)
                         )
 
                 if assign_unknown:
@@ -410,11 +407,9 @@ def assign_tp_lt(self, instruction_form):
 
     def _handle_instruction_found(self, instruction_data, port_number, instruction_form, flags):
         """Apply performance data to instruction if it was found in the archDB"""
-        throughput = instruction_data["throughput"]
-        port_pressure = self._machine_model.average_port_pressure(
-            instruction_data["port_pressure"]
-        )
-        instruction_form.port_uops = instruction_data["port_pressure"]
+        throughput = instruction_data.throughput
+        port_pressure = self._machine_model.average_port_pressure(instruction_data.port_pressure)
+        instruction_form.port_uops = instruction_data.port_pressure
         try:
             assert isinstance(port_pressure, list)
             assert len(port_pressure) == port_number
@@ -434,7 +429,7 @@ def _handle_instruction_found(self, instruction_data, port_number, instruction_f
             # assume 0 cy and mark as unknown
             throughput = 0.0
             flags.append(INSTR_FLAGS.TP_UNKWN)
-        latency = instruction_data["latency"]
+        latency = instruction_data.latency
         latency_wo_load = latency
         if latency is None:
             # assume 0 cy and mark as unknown