Include vector register check in register file

osaca/parser/memory.py

@@ -5,6 +5,7 @@
 
 class MemoryOperand(Operand):
     WILDCARD = "*"
+
     def __init__(
         self,
         offset=None,
@@ -129,14 +130,16 @@ def __str__(self):
     def __repr__(self):
         return self.__str__()
 
-    def equals(self, other, isa):
+    def is_mem_type(self, other, isa):
         if isa == "aarch64":
             if (
                 # check base
                 (
                     (self.base is None and other.base is None)
                     or other.base == self.WILDCARD
-                    or (isinstance(self.base, RegisterOperand) and (self.base.prefix == other.base))
+                    or (
+                        isinstance(self.base, RegisterOperand) and (self.base.prefix == other.base)
+                    )
                 )
                 # check offset
                 and (
@@ -180,7 +183,7 @@ def equals(self, other, isa):
             ):
                 return True
             return False
-        
+
         if isa == "x86":
             if (
                 # check base
@@ -202,7 +205,8 @@ def equals(self, other, isa):
                         self.offset is not None
                         and isinstance(self.offset, ImmediateOperand)
                         and (
-                            other.offset == "imd" or (other.offset is None and self.offset.value == "0")
+                            other.offset == "imd"
+                            or (other.offset is None and self.offset.value == "0")
                         )
                     )
                     or (isinstance(self.offset, IdentifierOperand) and other.offset == "id")
@@ -226,4 +230,3 @@ def equals(self, other, isa):
             ):
                 return True
             return False
-

osaca/parser/parser_x86att.py

@@ -18,6 +18,7 @@
 
 
 class ParserX86ATT(BaseParser):
+    WILDCARD = "*"
     _instance = None
 
     # Singelton pattern, as this is created very many times

osaca/parser/register.py

@@ -1,11 +1,9 @@
 #!/usr/bin/env python3
 
 from osaca.parser.operand import Operand
-from osaca.parser import ParserX86ATT
 
 
 class RegisterOperand(Operand):
-    WILDCARD = "*"
     def __init__(
         self,
         name=None,
@@ -165,7 +163,35 @@ def __str__(self):
     def __repr__(self):
         return self.__str__()
 
-    def equals(self, other, isa):
+    def is_vector_register(self):
+        """Check if register is a vector register"""
+        if self is None or self.name is None:
+            return False
+        if self.name.rstrip(string.digits).lower() in [
+            "mm",
+            "xmm",
+            "ymm",
+            "zmm",
+        ]:
+            return True
+        return False
+
+    def __eq__(self, other):
+        if isinstance(other, RegisterOperand):
+            return (
+                self._name == other._name
+                and self._width == other._width
+                and self._prefix == other._prefix
+                and self._regtype == other._regtype
+                and self._lanes == other._lanes
+                and self._shape == other._shape
+                and self._index == other._index
+                and self._mask == other._mask
+                and self._zeroing == other._zeroing
+            )
+        return False
+
+    def is_reg_type(self, other, isa, consider_masking=False):
         if isa == "aarch64":
             # check for wildcards
             if self.prefix == self.WILDCARD or other.prefix == self.WILDCARD:
@@ -209,8 +235,7 @@ def equals(self, other, isa):
             if i_reg_name == self.WILDCARD or self.name == self.WILDCARD:
                 return True
             # differentiate between vector registers (mm, xmm, ymm, zmm) and others (gpr)
-            parser_x86 = ParserX86ATT()
-            if parser_x86.is_vector_register(self):
+            if self.is_vector_register():
                 if self.name.rstrip(string.digits).lower() == i_reg_name:
                     # Consider masking and zeroing for AVX512
                     if consider_masking:
@@ -242,4 +267,4 @@ def equals(self, other, isa):
                     return True
                 if i_reg_name == "gpr":
                     return True
-            return False
+            return False

osaca/semantics/hw_model.py

@@ -261,10 +261,10 @@ def operand_to_class(self, o, new_operands):
         elif o["class"] == "prfop":
             new_operands.append(
                 PrefetchOperand(
-                type_id=o["type"] if "type" in o else None,
-                target=o["target"] if "target" in o else None,
-                policy=o["policy"] if "policy" in o else None,
-            )
+                    type_id=o["type"] if "type" in o else None,
+                    target=o["target"] if "target" in o else None,
+                    policy=o["policy"] if "policy" in o else None,
+                )
             )
         else:
             new_operands.append(o)
@@ -770,12 +770,12 @@ def _check_AArch64_operands(self, i_operand, operand):
         if isinstance(operand, RegisterOperand):
             if not isinstance(i_operand, RegisterOperand):
                 return False
-            return operand.equals(i_operand, self._data["isa"].lower())
+            return operand.is_reg_type(i_operand, self._data["isa"].lower())
         # memory
         if isinstance(operand, MemoryOperand):
             if not isinstance(i_operand, MemoryOperand):
                 return False
-            return operand.equals(i_operand, self._data["isa"].lower())
+            return operand.is_mem_type(i_operand, self._data["isa"].lower())
         # immediate
         if isinstance(i_operand, ImmediateOperand) and i_operand.imd_type == self.WILDCARD:
             return isinstance(operand, ImmediateOperand) and (operand.value is not None)

tests/test_parser_AArch64.py

@@ -234,7 +234,7 @@ def test_parse_line(self):
         instruction_form_5 = InstructionForm(
             mnemonic="prfm",
             operands=[
-                PrefetchOperand(type_id=["PLD"],target=["L1"],policy=["KEEP"]),
+                PrefetchOperand(type_id=["PLD"], target=["L1"], policy=["KEEP"]),
                 MemoryOperand(
                     offset=ImmediateOperand(value=2048),
                     base=RegisterOperand(prefix="x", name="26"),