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@stefandesouza
stefandesouza committed Dec 3, 2023
1 parent 93ae586 commit cef7f80
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Showing 12 changed files with 130 additions and 94 deletions.
39 changes: 26 additions & 13 deletions osaca/parser/parser_AArch64.py
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@
from osaca.parser.immediate import ImmediateOperand
from osaca.parser.condition import ConditionOperand


class ParserAArch64(BaseParser):
_instance = None

Expand Down Expand Up @@ -446,7 +447,7 @@ def process_sp_register(self, register):
new_reg = RegisterOperand(prefix_id="x", name="sp")
# reg["prefix"] = "x"
return new_reg

def process_condition(self, condition):
return ConditionOperand(ccode=condition.lower())

Expand Down Expand Up @@ -514,24 +515,32 @@ def process_immediate(self, immediate):
# normal integer value
immediate["type"] = "int"
# convert hex/bin immediates to dec
new_immediate = ImmediateOperand(type_id=immediate["type"], value_id=immediate["value"])
new_immediate = ImmediateOperand(
type_id=immediate["type"], value_id=immediate["value"]
)
new_immediate.value = self.normalize_imd(new_immediate)
return new_immediate
if "base_immediate" in immediate:
# arithmetic immediate, add calculated value as value
immediate["shift"] = immediate["shift"][0]
temp_immediate = ImmediateOperand(value_id=immediate["base_immediate"]["value"])
immediate["type"] = "int"
new_immediate = ImmediateOperand(type_id=immediate["type"], value_id=None, shift_id=immediate["shift"])
new_immediate.value = self.normalize_imd(temp_immediate) << int(immediate["shift"]["value"])
new_immediate = ImmediateOperand(
type_id=immediate["type"], value_id=None, shift_id=immediate["shift"]
)
new_immediate.value = self.normalize_imd(temp_immediate) << int(
immediate["shift"]["value"]
)
return new_immediate
if "float" in immediate:
dict_name = "float"
if "double" in immediate:
dict_name = "double"
if "exponent" in immediate[dict_name]:
immediate["type"] = dict_name
return ImmediateOperand(type_id=immediate["type"], value_id = immediate[immediate["type"]])
return ImmediateOperand(
type_id=immediate["type"], value_id=immediate[immediate["type"]]
)
else:
# change 'mantissa' key to 'value'
return ImmediateOperand(value_id=immediate[dict_name]["mantissa"], type_id=dict_name)
Expand All @@ -551,7 +560,11 @@ def process_identifier(self, identifier):
# remove value if it consists of symbol+offset
if "value" in identifier:
del identifier["value"]
return IdentifierOperand(name=identifier["name"] if "name" in identifier else None,offset=identifier["offset"] if "offset" in identifier else None, relocation=identifier["relocation"] if "relocation" in identifier else None)
return IdentifierOperand(
name=identifier["name"] if "name" in identifier else None,
offset=identifier["offset"] if "offset" in identifier else None,
relocation=identifier["relocation"] if "relocation" in identifier else None,
)

def get_full_reg_name(self, register):
"""Return one register name string including all attributes"""
Expand All @@ -568,16 +581,16 @@ def normalize_imd(self, imd):
"""Normalize immediate to decimal based representation"""
if isinstance(imd, IdentifierOperand):
return imd
if imd.value!=None and imd.type=="float":
if imd.value != None and imd.type == "float":

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osaca/parser/parser_AArch64.py#L584 

Comparison to None should be 'if cond is not None:' (E711)
return self.ieee_to_float(imd.value)
elif imd.value!=None and imd.type=="double":
elif imd.value != None and imd.type == "double":

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osaca/parser/parser_AArch64.py#L586 

Comparison to None should be 'if cond is not None:' (E711)
return self.ieee_to_float(imd.value)
elif imd.value!=None:
elif imd.value != None:

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osaca/parser/parser_AArch64.py#L588 

Comparison to None should be 'if cond is not None:' (E711)
if isinstance(imd.value, str):
# hex or bin, return decimal
return int(imd.value, 0)
else:
return imd.value
return imd.value
# identifier
return imd

Expand Down Expand Up @@ -608,10 +621,10 @@ def is_flag_dependend_of(self, flag_a, flag_b):
# we assume flags are independent of each other, e.g., CF can be read while ZF gets written
# TODO validate this assumption
if isinstance(flag_a, Operand):
return (flag_a.name == flag_b["name"])
return flag_a.name == flag_b["name"]
else:
return (flag_a["name"] == flag_b["name"])
return flag_a["name"] == flag_b["name"]

if flag_a.name == flag_b["name"]:
return True
return False
Expand Down
11 changes: 6 additions & 5 deletions osaca/parser/parser_x86att.py
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Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@
from osaca.parser.immediate import ImmediateOperand
from osaca.parser.operand import Operand

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Redefinition of unused 'Operand' from line 10 (F811)


class ParserX86ATT(BaseParser):
_instance = None

Expand Down Expand Up @@ -372,8 +373,8 @@ def process_immediate(self, immediate):
# actually an identifier, change declaration
return immediate
# otherwise just make sure the immediate is a decimal
#immediate["value"] = int(immediate["value"], 0)
new_immediate = ImmediateOperand(value_id = int(immediate["value"], 0))
# immediate["value"] = int(immediate["value"], 0)
new_immediate = ImmediateOperand(value_id=int(immediate["value"], 0))
return new_immediate

def get_full_reg_name(self, register):
Expand All @@ -385,7 +386,7 @@ def normalize_imd(self, imd):
"""Normalize immediate to decimal based representation"""
if isinstance(imd, IdentifierOperand):
return imd
if imd.value!=None:
if imd.value != None:

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Comparison to None should be 'if cond is not None:' (E711)
if isinstance(imd.value, str):
# return decimal
return int(imd.value, 0)
Expand All @@ -399,9 +400,9 @@ def is_flag_dependend_of(self, flag_a, flag_b):
# we assume flags are independent of each other, e.g., CF can be read while ZF gets written
# TODO validate this assumption
if isinstance(flag_b, Operand):
return (flag_a.name == flag_b.name)
return flag_a.name == flag_b.name
else:
return (flag_a.name == flag_b["name"])
return flag_a.name == flag_b["name"]
if flag_a.name == flag_b.name:
return True
return False
Expand Down
1 change: 0 additions & 1 deletion osaca/parser/register.py
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Original file line number Diff line number Diff line change
Expand Up @@ -144,7 +144,6 @@ def __str__(self):
def __repr__(self):
return self.__str__()


def __eq__(self, other):
if isinstance(other, RegisterOperand):
return (
Expand Down
5 changes: 4 additions & 1 deletion osaca/semantics/arch_semantics.py
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Original file line number Diff line number Diff line change
Expand Up @@ -313,7 +313,10 @@ def assign_tp_lt(self, instruction_form):
# since it is no mem store
if (
self._isa == "aarch64"
and not isinstance(instruction_form.semantic_operands["destination"], MemoryOperand)
and not isinstance(
instruction_form.semantic_operands["destination"],
MemoryOperand,
)
and all(
[
op.post_indexed or op.pre_indexed
Expand Down
40 changes: 25 additions & 15 deletions osaca/semantics/hw_model.py
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Original file line number Diff line number Diff line change
Expand Up @@ -77,7 +77,6 @@ def __init__(self, arch=None, path_to_yaml=None, isa=None, lazy=False):
if cached:
self._data = cached
else:

yaml = self._create_yaml_object()
# otherwise load
with open(self._path, "r") as f:
Expand Down Expand Up @@ -202,7 +201,7 @@ def operand_to_class(self, o, new_operands):
)
elif o["class"] == "memory":
if isinstance(o["base"], dict):
o["base"] = RegisterOperand(name = o["base"]["name"])
o["base"] = RegisterOperand(name=o["base"]["name"])
new_operands.append(
MemoryOperand(
base_id=o["base"],
Expand All @@ -224,7 +223,8 @@ def operand_to_class(self, o, new_operands):
)
)
elif o["class"] == "identifier":
new_operands.append(IdentifierOperand(
new_operands.append(
IdentifierOperand(
name=o["name"] if "name" in o else None,
source=o["source"] if "source" in o else False,
destination=o["destination"] if "destination" in o else False,
Expand Down Expand Up @@ -364,7 +364,6 @@ def get_load_throughput(self, memory):
return ld_tp.copy()
return [MemoryOperand(port_pressure=self._data["load_throughput_default"].copy())]


def get_store_latency(self, reg_type):
"""Return store latency for given register type."""
# assume 0 for now, since load-store-dependencies currently not detectable
Expand All @@ -377,8 +376,7 @@ def get_store_throughput(self, memory, src_reg=None):
st_tp = [
tp
for tp in st_tp
if "src" in tp
and self._check_operands(src_reg, RegisterOperand(name=tp["src"]))
if "src" in tp and self._check_operands(src_reg, RegisterOperand(name=tp["src"]))
]
if len(st_tp) > 0:
return st_tp.copy()
Expand Down Expand Up @@ -470,7 +468,7 @@ def dump(self, stream=None):
yaml = self._create_yaml_object()

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Local variable 'yaml' is assigned to but never used (F841)
if not stream:
stream = StringIO()
'''
"""
yaml.dump(
{
k: v
Expand All @@ -488,12 +486,18 @@ def dump(self, stream=None):
yaml.dump({"load_throughput": formatted_load_throughput}, stream)
yaml.dump({"instruction_forms": formatted_instruction_forms}, stream)
'''
"""
if isinstance(stream, StringIO):
return stream.getvalue()

def operand_to_dict(self, mem):
return {'base':mem.base, 'offset':mem.offset, 'index':mem.index, 'scale':mem.scale, 'port_pressure':mem.port_pressure}
return {
"base": mem.base,
"offset": mem.offset,
"index": mem.index,
"scale": mem.scale,
"port_pressure": mem.port_pressure,
}

######################################################

Expand Down Expand Up @@ -875,7 +879,11 @@ def _is_AArch64_mem_type(self, i_mem, mem):
and isinstance(mem.offset, IdentifierOperand)
and isinstance(i_mem.offset, IdentifierOperand)
)
or (mem.offset is not None and isinstance(mem.offset, ImmediateOperand) and isinstance(i_mem.offset, ImmediateOperand))
or (
mem.offset is not None
and isinstance(mem.offset, ImmediateOperand)
and i_mem.offset == "imd"
)
)
# check index
and (
Expand All @@ -896,7 +904,11 @@ def _is_AArch64_mem_type(self, i_mem, mem):
# check pre-indexing
and (i_mem.pre_indexed == self.WILDCARD or mem.pre_indexed == i_mem.pre_indexed)
# check post-indexing
and (i_mem.post_indexed == self.WILDCARD or mem.post_indexed == i_mem.post_indexed or (type(mem.post_indexed) == dict and i_mem.post_indexed == True))
and (
i_mem.post_indexed == self.WILDCARD
or mem.post_indexed == i_mem.post_indexed
or (type(mem.post_indexed) == dict and i_mem.post_indexed == True)

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Do not compare types, for exact checks use `is` / `is not`, for instance checks use `isinstance()` (E721)

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Comparison to True should be 'if cond is True:' or 'if cond:' (E712)
)
):
return True
return False
Expand All @@ -923,8 +935,7 @@ def _is_x86_mem_type(self, i_mem, mem):
mem.offset is not None
and isinstance(mem.offset, ImmediateOperand)
and (
i_mem.offset == "imd"
or (i_mem.offset is None and mem.offset.value == "0")
i_mem.offset == "imd" or (i_mem.offset is None and mem.offset.value == "0")
)
)
or (isinstance(mem.offset, IdentifierOperand) and i_mem.offset == "id")
Expand All @@ -946,7 +957,6 @@ def _is_x86_mem_type(self, i_mem, mem):
or (mem.scale != 1 and i_mem.scale != 1)
)
):

return True
return False

Expand Down
47 changes: 26 additions & 21 deletions osaca/semantics/isa_semantics.py
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Original file line number Diff line number Diff line change
Expand Up @@ -121,23 +121,27 @@ def assign_src_dst(self, instruction_form):
for operand in [op for op in op_dict["source"] if isinstance(op, MemoryOperand)]:
post_indexed = operand.post_indexed
pre_indexed = operand.pre_indexed
if post_indexed or pre_indexed or (isinstance(post_indexed, dict) and "value" in post_indexed):
if (
post_indexed
or pre_indexed
or (isinstance(post_indexed, dict) and "value" in post_indexed)
):
new_op = operand.base
new_op.pre_indexed = pre_indexed
new_op.post_indexed = post_indexed
op_dict["src_dst"].append(
new_op
)
op_dict["src_dst"].append(new_op)
for operand in [op for op in op_dict["destination"] if isinstance(op, MemoryOperand)]:
post_indexed = operand.post_indexed
pre_indexed = operand.pre_indexed
if post_indexed or pre_indexed or (isinstance(post_indexed, dict) and "value" in post_indexed):
if (
post_indexed
or pre_indexed
or (isinstance(post_indexed, dict) and "value" in post_indexed)
):
new_op = operand.base
new_op.pre_indexed = pre_indexed
new_op.post_indexed = post_indexed
op_dict["src_dst"].append(
new_op
)
op_dict["src_dst"].append(new_op)
# store operand list in dict and reassign operand key/value pair
instruction_form.semantic_operands = op_dict
# assign LD/ST flags
Expand Down Expand Up @@ -188,7 +192,11 @@ def get_reg_changes(self, instruction_form, only_postindexed=False):

if only_postindexed:
for o in instruction_form.operands:
if isinstance(o, MemoryOperand) and o.base != None and isinstance(o.post_indexed, dict):
if (
isinstance(o, MemoryOperand)
and o.base != None

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Comparison to None should be 'if cond is not None:' (E711)
and isinstance(o.post_indexed, dict)
):
base_name = (o.base.prefix if o.base.prefix != None else "") + o.base.name

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Comparison to None should be 'if cond is not None:' (E711)
return {
base_name: {
Expand Down Expand Up @@ -217,7 +225,7 @@ def get_reg_changes(self, instruction_form, only_postindexed=False):
if isa_data is not None and isa_data.operation is not None:
for i, o in enumerate(instruction_form.operands):
operand_name = "op{}".format(i + 1)

if isinstance(o, RegisterOperand):
o_reg_name = (o.prefix if o.prefix != None else "") + o.name
reg_operand_names[o_reg_name] = operand_name
Expand Down Expand Up @@ -251,15 +259,12 @@ def _apply_found_ISA_data(self, isa_data, operands):
op_dict["source"] = []
op_dict["destination"] = []
op_dict["src_dst"] = []

# handle dependency breaking instructions
if isa_data.breaks_dep and operands[1:] == operands[:-1]:
op_dict["destination"] += operands
if isa_data.hidden_operands!=[]:
op_dict["destination"] += [
hop
for hop in isa_data.hidden_operands
]
if isa_data.hidden_operands != []:
op_dict["destination"] += [hop for hop in isa_data.hidden_operands]
return op_dict

for i, op in enumerate(isa_data.operands):
Expand All @@ -272,9 +277,9 @@ def _apply_found_ISA_data(self, isa_data, operands):
if op.destination:
op_dict["destination"].append(operands[i])
continue

# check for hidden operands like flags or registers
if isa_data.hidden_operands!=[]:
if isa_data.hidden_operands != []:
# add operand(s) to semantic_operands of instruction form
for op in isa_data.hidden_operands:
if isinstance(op, Operand):
Expand All @@ -286,15 +291,15 @@ def _apply_found_ISA_data(self, isa_data, operands):
else "destination"
)
else:
dict_key = (
dict_key = (
"src_dst"
if op["source"] and op["destination"]
else "source"
if op["source"]
else "destination"
)
)
op_dict[dict_key].append(op)

return op_dict

def _has_load(self, instruction_form):
Expand Down
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