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os/board/rtl8730e: add driver layer implemenation for i2s tdm #6541

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@lhenry-realtek lhenry-realtek commented Nov 27, 2024

Add initial porting/os layer commit

  • TDM parameters fixed on I2S2 to generate required signal for AIS25BA
  • DMA is not tested and likely requires further implementation

Config:

- RTL8730E Peripheral Support:
    [*] AMEBASMART_I2C
    [*] Amebasmart I2S
    [*] I2S_2
    [*] Enable I2S RX
    [ ] Enable I2S TX
    [*] Enable I2S TDM Support
- Device Drivers:
    [*] I2C Driver Support
    [*] I2S Driver Support

Add initial porting/os layer commit
- TDM parameters fixed on I2S2 to generate required signal for AIS25BA
- DMA is not tested and likely requires further implementation

Config:
- RTL8730E Peripheral Support:
    [ ] AMEBASMART_I2C
    [*] Amebasmart I2S
    [*] I2S_2
    [*] Enable I2S RX
    [*] Enable I2S TDM Support
- Device Drivers:
    [ ] I2C Driver Support
    [*] I2S Driver Support
- Application Configuration > Examples:
    [*] I2S character driver test
    [*] Use I2S receiver
    [ ] Use I2S transmitter
    /dev/i2schar4 I2S character device path
Fix clock selection parameters to get targeted signal value:
MCLK = 12.288MHz (OK)
BCLK = 2.048MHz (OK)
WCLK (need to setup Rx api in order to trigger WCLK activity)
@lhenry-realtek
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MCLK/BCLK signal observed with LA and verified to be within parameters
WCLK is currently not generated as full RX api is not done yet as of 110a416

- WCLK was not started because there was no I2S and DMA transaction being started, added calls to relevant APIs
- Currently DMA for I2S TDM is not properly initialized and will hardfault when rx page, currently under investigation
- User is required to call I2S_RESUME and I2S_PAUSE macros when attempting a TDM operation (e.g READ), as these macros will start WCLK (for MASTER mode)
- Add some debug logging and revert changes to irrelevant files
@lhenry-realtek
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Logic_mcpxc0K5UQ

BCLK(green) is 2.048MHz, WCLK(blue) is properly generated at 16kHz when I2S_RESUME is called before an I2S_READ. The break at the end is due to hardfault, which is currently being investigated

Pin allocation is adjusted for TDM functionality - please refer to email chain for rework steps for first board revision (Dec 2024)

Please note that as a result of this change, a new pinmux configuration needs to be maintained for TDM only!

- PB29 (previously I2C0 SDA) --> I2S2 DIN0
- PA30 [or PB5] (previously unconnected) --> I2C0 SDA
- PB20 (previously I2S2 DIN0) --> Unconnected
This commit completes the DMA portion of the I2S implementation and allows for receive of data based on AIS25BA sensor TDM signal specification

Please note that if TDM board v1 (Dec 2024) is used, rework is required!

To test, build with AIS25BA sensor example and use "sensor" command in TASH
@lhenry-realtek lhenry-realtek marked this pull request as ready for review December 23, 2024 10:19
I2C2 pins (PB10, PB11) are used instead of existing I2C0, pinmux change is updated.

Verified working on TDM board for PoC
TDM RX will keep PM lock until DMA transfer is complete, then release the lock in ISR

Verified on TDM board by removing delay causing tash to sleep instantly, then use pm_resume to enable board to sleep. While asleep, run sensor test command
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PM for I2S TDM sample output:

rCA32PG-KM4PG-Wakeup : UART LOG
i2s_getdefaultconfig: init for tdm: 1
i2s_tdm_set_param: in TDM set_param!

TASH>>Sensor test!!
cmd 2567 arg 32000, aa:2567
sample rate 32000
i2s_samplerate: called by ioctl!
i2s_samplerate: tdm sample rate currently not changeable!
Read from MEMS sensor
add       19, freq 100000, len7
data read is       20
data read 0B :        0
data read 26 :        0
data read 2F :       e1
data read 30 :        f
data read 2E :       32
data read 0B :        0
data read 26 :        0
data read 2F :       e1
data read 30 :        f
data read 2E :       32
ais25ba_read_i2s: apb alloc
ais25ba_read_i2s: before i2s receive
ais25ba_read_i2s: i2s receive return 0
sensor test complete
i2s_transfer_rx_handleirq: handle irq
i2s_transfer_rx_handleirq: handle irq
i2s_transfer_rx_handleirq: rx complete 8CH! stopping clockgen! APB: 0x60152f50
ameba_i2s_tdm_pause: in pause
i2s_rx_worker: rx.act.head=0 rx.done.head=0x6013c948
ais25ba_i2s_callback: in callback..........................................
ais25ba_i2s_callback: apb=0x60152f50 nbytes=512 result=0
AIS25BA RX (0x60152f72):
0000: fffffffffffffeffc440ff7fffffffff ffffffffffffffff58214728039dffff .........@...... ........X!G(....
0020: ffffffffffffffffebe5cdbd0bf1ffff fffffffffffffeffe5fc2dfa83e8ffff ................ ..........-.....
0040: ffffffffffffffffdcfe6f1127d9ffff ffffffffffffffff53f6c9fc2bdfffff ..........o.'... ........S...+...
0060: fffffffffffffffff3f641f9a3e3ffff ffffffffffffffffb2f93101e3e0ffff ..........A..... ..........1.....
0080: ffffffffffffffff04f91d01bfdfffff ffffffffffffffff37f869fec7e0ffff ................ ........7.i.....
00a0: ffffffffffffffff97f8e7feebe0ffff ffffffffffffffffc9f8b9ff93e0ffff ................ ................
00c0: ffffffffffffffffa1f86fff9fe0ffff ffffffffffffffff99f835ffc3e0ffff ..........o..... ..........5.....
00e0: ffffffffffffffffa5f85fffb3e0ffff ffffffffffffffffa1f875ffb3e0ffff .........._..... ..........u.....
0100: ffffffffffffffffa1f85dffbfe0ffff ffffffffffffffffaff851ffbbe0ffff ..........]..... ..........Q.....
0120: ffffffffffffffffabf85bffafe0ffff ffffffffffffffff9bf857ffabe0ffff ..........[..... ..........W.....
0140: ffffffffffffffff9bf857ffa7e0ffff ffffffffffffffffa3f85fff9be0ffff ..........W..... .........._.....
0160: ffffffffffffffff9bf85fffa7e0ffff ffffffffffffffff9bf85dffc3e0ffff .........._..... ..........].....
0180: ffffffffffffffff9df859ffc7e0ffff ffffffffffffffff9bf853ffb7e0ffff ..........Y..... ..........S.....
01a0: ffffffffffffffff9ff84fffbbe0ffff ffffffffffffffff9bf849ffbbe0ffff ..........O..... ..........I.....
01c0: ffffffffffffffff91f851ffa7e0ffff ffffffffffffffff93f863ff97e0ffff ..........Q..... ..........c.....
01e0: ffffffffffffffff99f873ffa3e0ffff ffffffffffffffff9bf867ffbfe0ffff ..........s..... ..........g.....
i2s_rx_worker: before apb_free!
i2s_rx_worker: after apb_free!
CA32PG-KM4PG-Wakeup : UART LOG

…bility of TDM

Parameters to setup TDM are now configured from amebasmart_i2s.c OS layer, there is currently no error handling if clock setting is invalid

MCLK in i2s_clock_select is also currently fixed until a better way to configure it is found
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