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Fixup whitespace
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amykyta3 committed Jan 6, 2024
1 parent 6a550ab commit 0d39774
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Showing 4 changed files with 7 additions and 5 deletions.
2 changes: 1 addition & 1 deletion src/peakrdl_regblock/__about__.py
Original file line number Diff line number Diff line change
@@ -1 +1 @@
__version__ = "0.19.0"
__version__ = "0.20.0"
7 changes: 4 additions & 3 deletions src/peakrdl_regblock/module_tmpl.sv
Original file line number Diff line number Diff line change
Expand Up @@ -135,12 +135,12 @@ module {{ds.module_name}} (
always_comb begin
{%- if ds.has_external_addressable %}
automatic logic is_external = '0;
{% endif %}
{%- endif %}
{{address_decode.get_implementation()|indent(8)}}
{%- if ds.has_external_addressable %}
decoded_strb_is_external = is_external;
external_req = is_external;
{% endif %}
{%- endif %}
end

// Pass down signals to next stage
Expand Down Expand Up @@ -251,7 +251,7 @@ module {{ds.module_name}} (
logic readback_err;
logic readback_done;
logic [{{cpuif.data_width-1}}:0] readback_data;
{{readback_implementation|indent}}
{{readback_implementation|indent}}
{% if ds.retime_read_response %}
always_ff {{get_always_ff_event(cpuif.reset)}} begin
if({{get_resetsignal(cpuif.reset)}}) begin
Expand Down Expand Up @@ -283,3 +283,4 @@ module {{ds.module_name}} (
assign cpuif_rd_err = readback_err;
{%- endif %}
endmodule
{# (eof newline anchor) #}
1 change: 1 addition & 0 deletions src/peakrdl_regblock/package_tmpl.sv
Original file line number Diff line number Diff line change
Expand Up @@ -8,3 +8,4 @@ package {{ds.package_name}};

{{hwif.get_package_contents()|indent}}
endpackage
{# (eof newline anchor) #}
2 changes: 1 addition & 1 deletion src/peakrdl_regblock/write_buffering/template.sv
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ always_ff {{get_always_ff_event(cpuif.reset)}} begin
{%- endif %}
end
{%- endfor %}
{% if is_own_trigger %}
{%- if is_own_trigger %}
{{wbuf_prefix}}.trigger_q <= {{wbuf.get_raw_trigger(node)}};
{%- endif %}
end
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