cts: include ADDITIONAL_LIBS in variables to CTS stage

This is not strictly necessary for the execution of this stage, but it is useful, otherwise .lib files are not included in make cts_issue Signed-off-by: Øyvind Harboe <[email protected]>
The-OpenROAD-Project · Mar 22, 2024 · 2f1c989 · 2f1c989
1 parent 896154c
commit 2f1c989
Showing 1 changed file with 21 additions and 8 deletions.
diff --git a/openroad.bzl b/openroad.bzl
@@ -178,6 +178,7 @@ def build_openroad(
 
     x = map(lambda ext: map2(lambda m: "//:results/" + platform + "/%s/%s/%s.%s" % (m, macro_variants.get(m, macro_variant), m, ext), macros), ["lef", "lib"])
     macro_lef_targets, macro_lib_targets = x
+    # macro_gds_targets = map(lambda m: "//:results/" + platform + "/%s/%s/6_final.gds" % (m, macro_variants.get(m, macro_variant)), macros)
 
     stage_sources = dict(stage_sources)
 
@@ -197,22 +198,24 @@ def build_openroad(
 
     lefs_args = (["ADDITIONAL_LEFS=" + ADDITIONAL_LEFS] if len(macros) > 0 else [])
     libs_args = (["ADDITIONAL_LIBS=" + ADDITIONAL_LIBS] if len(macros) > 0 else [])
-    gds_args = (["ADDITIONAL_GDS_FILES=" + ADDITIONAL_GDS_FILES] if len(macros) > 0 else [])
+    # gds_args = (["ADDITIONAL_GDS_FILES=" + ADDITIONAL_GDS_FILES] if len(macros) > 0 else [])
 
-    stage_args["synth"] = stage_args.get("synth", []) + libs_args + [
+    stage_args["synth"] = stage_args.get("synth", []) + [
         "VERILOG_FILES=" + " ".join(set(verilog_files)),
         "SDC_FILE_CLOCK_PERIOD=" + SDC_FILE_CLOCK_PERIOD,
     ]
-    stage_args["floorplan"] = stage_args.get("floorplan", []) + lefs_args + libs_args + (
+    stage_args["floorplan"] = stage_args.get("floorplan", []) + (
         [] if len(macros) == 0 else [
             "CORE_MARGIN=4",
             "'PDN_TCL=\\$${PLATFORM_DIR}/openRoad/pdn/BLOCKS_grid_strategy.tcl'",
         ]
     ) + io_constraints_args + (["MACROS=" + " ".join(set(macros))] if len(macros) > 0 else [])
 
-    stage_args["place"] = stage_args.get("place", []) + libs_args + io_constraints_args
+    stage_args["place"] = stage_args.get("place", []) + io_constraints_args
 
-    stage_args["final"] = stage_args.get("final", []) + gds_args + lefs_args + (
+    stage_args["cts"] = stage_args.get("cts", [])
+
+    stage_args["final"] = stage_args.get("final", []) + (
         ["GND_NETS_VOLTAGES=\"\"", "PWR_NETS_VOLTAGES=\"\""]
     ) + (
         ["GDS_ALLOW_EMPTY=(" + "|".join(macros) + ")"] if len(macros) > 0 else []
@@ -225,8 +228,12 @@ def build_openroad(
         ]
     )
 
+    for stage in ["synth", "floorplan", "place", "cts", "grt", "route", "final"]:
+        stage_args[stage] = stage_args.get(stage, []) + libs_args
+        stage_sources[stage] = stage_sources.get(stage, []) + macro_lib_targets
+
     abstract_source = str(name_to_stage[mock_stage]) + "_" + mock_stage
-    stage_args["generate_abstract"] = stage_args.get("generate_abstract", []) + gds_args + lefs_args + (
+    stage_args["generate_abstract"] = stage_args.get("generate_abstract", []) + (
         ["ABSTRACT_SOURCE=" + abstract_source] if mock_abstract else []
     )
 
@@ -340,13 +347,19 @@ def build_openroad(
         )
 
     stage_sources["route"] = stage_sources.get("route", []) + outs["cts"]
+    for stage in ["floorplan", "final", "generate_abstract"]:
+        stage_args[stage] = stage_args.get(stage, []) + lefs_args
+        stage_sources[stage] = stage_sources.get(stage, []) + macro_lef_targets
+
+    # FIXME for mock abstracts, we don't have .gds files. How can we know if there is a .gds file for a macro?
+    # for stage in ["final", "generate_abstract"]:
+    #     stage_args[stage] = stage_args.get(stage, []) + gds_args
+    #     stage_sources[stage] = stage_sources.get(stage, []) + macro_gds_targets
 
     for stage in stages:
         make_pattern = Label("//:" + stage + "-bazel.mk")
         stage_sources[stage] = ([make_pattern] +
                                 all_sources +
-                                (macro_lib_targets if stage not in ("clock_period", "synth_sdc") else []) +
-                                (macro_lef_targets if stage not in ("synth", "clock_period", "synth_sdc") else []) +
                                 stage_sources.get(stage, []))
         stage_args[stage] = ["make"] + ["MAKE_PATTERN=$(location " + str(make_pattern) + ")"] + base_args + stage_args.get(stage, [])