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Aem boot delay fix #17
base: aem-4.17.4
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Commits on Sep 16, 2024
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xen/arch/x86/slaunch.c: Map the TPM event log after TXT regions
Map the TPM event log after the TXT regions are mapped to avoid an early page fault when booting with slaunch. Signed-off-by: Michał Żygowski <[email protected]>
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xen/arch/x86/intel_txt.c: Disable MTRRs before restoring them on BSP
Right now the MTRRs were restored in an ugly way, while MTRR enable bit was set and caching was not disabled. Mimic the generic Xen MTRR driver behavior when changing MTRRs. Signed-off-by: Michał Żygowski <[email protected]>
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xen/arch/x86/e820.c: Read the MTRR caps and default type after restoring
The MTRR capabilities and default type were read before the MTRRs were restored in slaunch flow. The restoration itself updated the MTRR default type MSR, so the mtrr_top_of_ram had invalid state in mtrr_cap and mtrr_def variables. Move reading those MSRs after MTRRs are restored in slaunch flow. Signed-off-by: Michał Żygowski <[email protected]>
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arch/x86/hvm/vmx/vmcs.c: Check for VMX in SMX while slaunch active
Do the check if IA32_FEATURE_CONTROL has the proper bits enabled to run VMX in SMX when slaunch is active. Signed-off-by: Michał Żygowski <[email protected]>
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xen/arch/x86/boot/head.S: Use MAXPHYADDR fr MTRR masks in MLE capabil…
…ities The bootloader should prepare the MTRR masks using MAXPHYADDRs. On modern Intel platforms, the SINIT ACM forces this bit to be 1 according to TXT MLE Software Development Guide Revision 017.4. Signed-off-by: Michał Żygowski <[email protected]>
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xen/arch/x86/boot/head.S: Set CBnT support capability in MLE
Signed-off-by: Michał Żygowski <[email protected]>
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xen/arch/x86/intel_txt.c: Restore IA32_MISC_ENABLES
Signed-off-by: Michał Żygowski <[email protected]>
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xen/arch/x86/cpu/intel.c: Report SMX and TXT capabilities
Report the SMX and TXT capabilitiesso that dom0 can query the Intel TXT support information using xl dmesg. Signed-off-by: Michał Żygowski <[email protected]>
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