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Merge pull request #53 from XavierAubert/cv32e40p/dev
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up to date with latest OHG/ dev
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dd-baoshan authored Sep 14, 2023
2 parents 4b90422 + 1acda87 commit ac85d5d
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Showing 13 changed files with 1,731 additions and 18 deletions.
6 changes: 1 addition & 5 deletions cv32e40p/env/corev-dv/cv32e40p_instr_gen_config.sv
Original file line number Diff line number Diff line change
Expand Up @@ -142,11 +142,7 @@ class cv32e40p_instr_gen_config extends riscv_instr_gen_config;
}

constraint xpulp_instr_in_debug_rom_c {
if($test$plusargs("include_xpulp_instr_in_debug_rom")) {
xpulp_instr_in_debug_rom dist {0 := 1, 1 := 2};
} else {
xpulp_instr_in_debug_rom == 0;
}
xpulp_instr_in_debug_rom dist {0 := 1, 1 := 2};
}

constraint str_rs1_rs3_c {
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4 changes: 2 additions & 2 deletions cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv
Original file line number Diff line number Diff line change
Expand Up @@ -157,13 +157,13 @@ class cv32e40p_rand_instr_stream extends riscv_rand_instr_stream;

//Use this plusarg - include_xpulp_instr_in_debug_rom to include xpulp instr
//In random debug_rom instructions. Added for v2 debug tests with xpulp.
if (cv32e40p_cfg.xpulp_instr_in_debug_rom && is_debug_program) begin
if (cv32e40p_cfg.xpulp_instr_in_debug_rom && is_debug_program && $test$plusargs("include_xpulp_instr_in_debug_rom")) begin
foreach(instr_list[i]) begin
randcase
1: randomize_debug_rom_instr(.instr(instr_list[i]), .is_in_debug(is_debug_program), .disable_dist());
2: randomize_instr(instr_list[i], is_debug_program);
endcase
`uvm_info("cv32e40p_rand_instr_stream", $sformatf("add_xpulp_instr_in_debug_rom set- Including xpulp instr in debug_rom"), UVM_LOW)
`uvm_info("cv32e40p_rand_instr_stream", $sformatf("include_xpulp_instr_in_debug_rom set- Including xpulp instr in debug_rom"), UVM_LOW)
end
end
else begin
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2 changes: 1 addition & 1 deletion cv32e40p/tests/programs/custom/coremark/core_portme.c
Original file line number Diff line number Diff line change
Expand Up @@ -100,5 +100,5 @@ get_time(void)
secs_ret
time_in_secs(CORE_TICKS ticks)
{
return ticks; // NB! Not implemented. Score is derivable from cycle count.
return ticks*1E-6; // Normalized to 1 MHz clock period
}
6 changes: 3 additions & 3 deletions cv32e40p/tests/programs/custom/coremark/test.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -12,8 +12,8 @@ default_cflags: >
-static
-pedantic
-DPERFORMANCE_RUN=1
-DITERATIONS=1
-DHAS_STDIO=1 -DHAS_PRINTF=1
-DFLAGS_STR=\""-mabi=ilp32 -march=rv32im -O3 -falign-functions=16 -funroll-all-loops -falign-jumps=4 -finline-functions -Wall -pedantic -nostartfiles -static -DPERFORMANCE_RUN=1 -DITERATIONS=1 -DHAS_STDIO=1 -DHAS_PRINTF=1"\"
-DITERATIONS=30
-DHAS_STDIO=1 -DHAS_PRINTF=1 -DHAS_FLOAT=1
-DFLAGS_STR=\""-mabi=ilp32 -march=rv32im -O3 -falign-functions=16 -funroll-all-loops -falign-jumps=4 -finline-functions -Wall -pedantic -nostartfiles -static -DPERFORMANCE_RUN=1 -DITERATIONS=30 -DHAS_STDIO=1 -DHAS_PRINTF=1 -DHAS_FLOAT=1"\"
description: >
Runs the CoreMark benchmark
Original file line number Diff line number Diff line change
Expand Up @@ -70,15 +70,15 @@ test1:
li x17, 0
li x18, 0

.align 4
.balign 4

cv.counti 1, 10
cv.endi 1, endO_1
cv.starti 1, startO_1
cv.endi 0, endZ_1
cv.starti 0, startZ_1
startO_1:
cv.counti 0, 10
startO_1:

.option norvc

Expand All @@ -87,7 +87,7 @@ startZ_1:
addi x17, x17, 1
addi x17, x17, 1
endZ_1:
addi x18, x18, 2
cv.counti 0, 10
addi x18, x18, 2
endO_1:

Expand All @@ -97,7 +97,7 @@ endO_1:
beq x20, x17, test1_1
c.addi x15, 0x1
test1_1:
li x21, 40
li x21, 20
beq x21, x18, test2
c.addi x15, 0x1

Expand All @@ -116,7 +116,7 @@ test2:
4: auipc x9, %pcrel_hi(startZ_2)
addi x9, x9, %pcrel_lo(4b)

.align 4
.balign 4

cv.count 1, x5
cv.end 1, x6
Expand Down Expand Up @@ -152,7 +152,7 @@ test3:
li x17, 0
li x18, 0

.align 4
.balign 4

cv.setupi 1, 10, endO_3
startO_3:
Expand Down Expand Up @@ -186,7 +186,7 @@ test4:

li x5, 10

.align 4
.balign 4

cv.setup 1, x5, endO_4
startO_4:
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