[TestDesignTools] Check return value

Signed-off-by: Eddie Hung <[email protected]>
Xilinx · Dec 24, 2024 · 4fd44cb · 4fd44cb
1 parent d6e7b42
commit 4fd44cb
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Showing 3 changed files with 6 additions and 6 deletions.
diff --git a/test/src/com/xilinx/rapidwright/eco/TestECOTools.java b/test/src/com/xilinx/rapidwright/eco/TestECOTools.java
@@ -187,7 +187,7 @@ public void testConnectNetSwapSinks() {
         EDIFNetlist netlist = design.getNetlist();
         Map<Net, Set<SitePinInst>> deferredRemovals = new HashMap<>();
 
-        DesignTools.updatePinsIsRouted(design);
+        Assertions.assertEquals(0, DesignTools.updatePinsIsRouted(design));
 
         // Disconnect the ILA inputs
         List<EDIFHierPortInst> disconnectPins = new ArrayList<>();
@@ -253,7 +253,7 @@ public void testConnectNetSwapSource() {
         EDIFNetlist netlist = design.getNetlist();
         Map<Net, Set<SitePinInst>> deferredRemovals = new HashMap<>();
 
-        DesignTools.updatePinsIsRouted(design);
+        Assertions.assertEquals(0, DesignTools.updatePinsIsRouted(design));
 
         // Disconnect the outputs
         List<EDIFHierPortInst> disconnectPins = new ArrayList<>();
@@ -386,7 +386,7 @@ public void testCreateCell() {
         Design design = RapidWrightDCP.loadDCP("picoblaze_ooc_X10Y235.dcp");
         EDIFNetlist netlist = design.getNetlist();
 
-        DesignTools.updatePinsIsRouted(design);
+        Assertions.assertEquals(0, DesignTools.updatePinsIsRouted(design));
 
         EDIFCell reference = netlist.getCell("kcpsm6");
         List<String> instNames = Arrays.asList("processor2", "processor3");
@@ -474,7 +474,7 @@ public void testCreateNet() {
         Design design = RapidWrightDCP.loadDCP("picoblaze_ooc_X10Y235.dcp");
         EDIFNetlist netlist = design.getNetlist();
 
-        DesignTools.updatePinsIsRouted(design);
+        Assertions.assertEquals(0, DesignTools.updatePinsIsRouted(design));
 
         List<String> netNames = Arrays.asList("processor/foo", "your_program/bar");
         ECOTools.createNet(design, netNames);

diff --git a/test/src/com/xilinx/rapidwright/interchange/TestPhysNetlistWriter.java b/test/src/com/xilinx/rapidwright/interchange/TestPhysNetlistWriter.java
@@ -331,7 +331,7 @@ public void testSimulateSwappedLutPinsWithRWRoute(String path, @TempDir Path tem
             inputDesign = null;
 
             Assertions.assertTrue(LUTTools.swapLutPinsFromPIPs(outputDesign) > 0);
-            DesignTools.updatePinsIsRouted(outputDesign);
+            Assertions.assertEquals(0, DesignTools.updatePinsIsRouted(outputDesign));
             TestRWRoute.assertAllSourcesRoutedFlagSet(outputDesign);
             TestRWRoute.assertAllPinsRouted(outputDesign);
             VivadoToolsHelper.assertFullyRouted(outputDesign);

diff --git a/test/src/com/xilinx/rapidwright/rwroute/TestGlobalSignalRouting.java b/test/src/com/xilinx/rapidwright/rwroute/TestGlobalSignalRouting.java
@@ -339,7 +339,7 @@ public void testSymmetricClkRouting() {
                     if (node != null) used.add(node);
                 }
             }
-            DesignTools.updatePinsIsRouted(net);
+            Assertions.assertEquals(0, DesignTools.updatePinsIsRouted(net));
             for (SitePinInst spi : net.getPins()) {
                 Assertions.assertTrue(spi.isRouted());
             }