refactoring and moving log computations to cpp compile side

Xilinx · Sep 18, 2024 · 337dced · 337dced
1 parent 8e297d1
commit 337dced
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Showing 4 changed files with 454 additions and 381 deletions.
diff --git a/src/finn/custom_op/fpgadataflow/hls/iodma_hls.py b/src/finn/custom_op/fpgadataflow/hls/iodma_hls.py
@@ -236,7 +236,7 @@ def docompute(self):
             raise ValueError("Invalid IODMA direction, please set to in or out")
         # define templates for instantiation
         dma_inst_template = func + "<DataWidth1, NumBytes1>(%s, %s, numReps);"
-        dwc_inst_template = dwc_func + "<%d, %d, %d, %d, %d, %d, %d, %d>(%s, %s, numReps);"
+        dwc_inst_template = dwc_func + "<%d, %d, %d, %d, %d>(%s, %s, numReps);"
         # do stream infrastructure and instantiations
         intfw = self.get_nodeattr("intfWidth")
         strmw = self.get_nodeattr("streamWidth")
@@ -257,10 +257,6 @@ def docompute(self):
             if outWidth > inWidth:
                 totalIters += int(np.floor(outWidth / inWidth) + 1) - 1
 
-            NumInWordsLog = int(np.log2(numInWords) + 1)
-            NumOutWordsLog = int(np.log2(numOutWords) + 1)
-            BufferWidthLog = int(np.log2(inWidth + outWidth) + 1)
-
             # AXI MM -> IODMA -> (DWCs) -> out
             # DWCs depend on AXI MM and out interface width
             if strmw == intfw:
@@ -281,9 +277,6 @@ def docompute(self):
                         outWidth,
                         numInWords,
                         numOutWords,
-                        NumInWordsLog,
-                        NumOutWordsLog,
-                        BufferWidthLog,
                         totalIters,
                         "dma2dwc",
                         "out_" + self.hls_sname(),
@@ -301,10 +294,6 @@ def docompute(self):
             if outWidth > inWidth:
                 totalIters += int(np.floor(outWidth / inWidth) + 1) - 1
 
-            NumInWordsLog = int(np.log2(numInWords) + 1)
-            NumOutWordsLog = int(np.log2(numOutWords) + 1)
-            BufferWidthLog = int(np.log2(inWidth + outWidth) + 1)
-
             # in0 -> (DWCs) -> IODMA -> AXI MM
             # DWCs depend on AXI MM and out interface width
             if strmw == intfw:
@@ -324,9 +313,6 @@ def docompute(self):
                         outWidth,
                         numInWords,
                         numOutWords,
-                        NumInWordsLog,
-                        NumOutWordsLog,
-                        BufferWidthLog,
                         totalIters,
                         "in0_" + self.hls_sname(),
                         "dwc2dma",

diff --git a/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py b/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py
@@ -41,7 +41,7 @@
 
 
 class StreamingDataWidthConverter_hls(StreamingDataWidthConverter, HLSBackend):
-    """Class that corresponds to finn-hlslib StreamingDataWidthConverter_Batch
+    """Class that corresponds to finn-hlslib StreamingDataWidthConverterGeneralized_Batch
     function."""
 
     def get_nodeattr_types(self):
@@ -77,18 +77,12 @@ def defines(self, var):
         if outWidth > inWidth:
             totalIters += int(np.floor(outWidth / inWidth) + 1) - 1
 
-        NumInWordsLog = int(np.log2(numInWords) + 1)
-        NumOutWordsLog = int(np.log2(numOutWords) + 1)
-        BufferWidthLog = int(np.log2(inWidth + outWidth) + 1)
 
         self.code_gen_dict["$DEFINES$"] = [
             "#define InWidth %d " % inWidth,
             "#define OutWidth %d " % outWidth,
             "#define NumInWords %d " % numInWords,
             "#define NumOutWords %d " % numOutWords,
-            "#define NumInWordsLog %d " % NumInWordsLog,
-            "#define NumOutWordsLog %d " % NumOutWordsLog,
-            "#define BufferWidthLog %d " % BufferWidthLog,
             "#define totalIters %d " % totalIters,
             "#define numReps %d" % numReps,
         ]
@@ -109,11 +103,10 @@ def strm_decl(self):
 
     def docompute(self):
         # TODO continue with fxns below, they are copy-pasted
-        op = "StreamingDataWidthConverter_Batch"
+        op = "StreamingDataWidthConverterGeneralized_Batch"
 
         self.code_gen_dict["$DOCOMPUTE$"] = [
             "%s<InWidth, OutWidth, NumInWords,NumOutWords," % op
-            + "NumInWordsLog, NumOutWordsLog, BufferWidthLog,"
             + " totalIters>(in0_%s, out_%s, numReps);" % (self.hls_sname(), self.hls_sname())
         ]