Minor fixes for DynMatMul mem_mode and inFIFODepths for getting throu…

…gh endtoend bert flow for EoY goal
Xilinx · Dec 18, 2024 · 6479daa · 6479daa
1 parent af849a1
commit 6479daa
Showing 1 changed file with 3 additions and 4 deletions.
diff --git a/src/finn/custom_op/fpgadataflow/rtl/dynmvau_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/dynmvau_rtl.py
@@ -46,12 +46,11 @@ def __init__(self, onnx_node, **kwargs):
         super().__init__(onnx_node, **kwargs)
 
     def get_nodeattr_types(self):
-        my_attrs = {
-            "inFIFODepths": ("ints", False, [2, 2]),
-        }
-
+        my_attrs = {}
         my_attrs.update(MVAU.get_nodeattr_types(self))
         my_attrs.update(RTLBackend.get_nodeattr_types(self))
+        my_attrs["inFIFODepths"] = ("ints", False, [2, 2])
+        my_attrs["mem_mode"] = ("s", False, "external", {"external"})
         return my_attrs
 
     def generate_params(self, model, path):