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1. cv32e41p cv32e41p Public

   Forked from openhwgroup/cv32e41p

   4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

   SystemVerilog

2. cv32e40p cv32e40p Public

   Forked from openhwgroup/cv32e40p

   CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

   SystemVerilog

3. core-v-verif core-v-verif Public

   Forked from openhwgroup/core-v-verif

   Functional verification project for the CORE-V family of RISC-V cores.

   Assembly