Merge pull request #163 from yrabbit/gw1ns-2-1

stage2. Add PLL support for GW1NS-2 chips

apycula/chipdb.py

@@ -182,6 +182,9 @@ def fse_pll(device, fse, ttyp):
             bel = bels.setdefault('RPLLA', Bel())
         elif ttyp == 89:
             bel = bels.setdefault('RPLLB', Bel())
+    elif device in {'GW1NS-2'}:
+        if ttyp in {87}:
+            bel = bels.setdefault('RPLLA', Bel())
     elif device in {'GW1NS-4'}:
         if ttyp in {88, 89}:
             bel = bels.setdefault('PLLVR', Bel())
@@ -453,6 +456,9 @@ def fse_fill_logic_tables(dev, fse):
  'GW1NZ-1':
    {'TRPLL0CLK0': (0, 17, 'F4'), 'TRPLL0CLK1': (0, 17, 'F5'),
     'TRPLL0CLK2': (0, 17, 'F6'), 'TRPLL0CLK3': (0, 17, 'F7'), },
+ 'GW1NS-2':
+   {'TRPLL0CLK0': (5, 19, 'F4'), 'TRPLL0CLK1': (5, 19, 'F7'),
+    'TRPLL0CLK2': (5, 19, 'F5'), 'TRPLL0CLK3': (5, 19, 'F6'), },
  'GW1N-4':
    {'TLPLL0CLK0': (0, 9, 'F4'), 'TLPLL0CLK1': (0, 9, 'F7'),
     'TLPLL0CLK2': (0, 9, 'F6'), 'TLPLL0CLK3': (0, 9, 'F5'),
@@ -482,7 +488,7 @@ def fse_create_pll_clock_aliases(db, device):
             for w_dst, w_srcs in db.grid[row][col].clock_pips.items():
                 for w_src in w_srcs.keys():
                     # XXX
-                    if device in {'GW1N-1', 'GW1NZ-1', 'GW1NS-4', 'GW1N-4', 'GW1N-9C', 'GW1N-9'}:
+                    if device in {'GW1N-1', 'GW1NZ-1', 'GW1NS-2', 'GW1NS-4', 'GW1N-4', 'GW1N-9C', 'GW1N-9'}:
                         if w_src in _pll_loc[device].keys():
                             db.aliases[(row, col, w_src)] = _pll_loc[device][w_src]
 
@@ -692,7 +698,14 @@ def dat_portmap(dat, dev, device):
                     for idx, nam in _pll_inputs:
                         wire = wirenames[dat['PllIn'][idx]]
                         off = dat['PllInDlt'][idx] * offx
-                        if off == 0:
+                        if device in {'GW1NS-2'}:
+                            # NS-2 is a strange thingy
+                            if nam in {'RESET', 'RESET_P', 'IDSEL1', 'IDSEL2', 'ODSEL5'}:
+                                bel.portmap[nam] = f'rPLL{nam}{wire}'
+                                dev.aliases[row, col, f'rPLL{nam}{wire}'] = (9, col, wire)
+                            else:
+                                bel.portmap[nam] = wire
+                        elif off == 0:
                             bel.portmap[nam] = wire
                         else:
                             # not our cell, make an alias
@@ -701,7 +714,7 @@ def dat_portmap(dat, dev, device):
                     for idx, nam in _pll_outputs:
                         wire = wirenames[dat['PllOut'][idx]]
                         off = dat['PllOutDlt'][idx] * offx
-                        if off == 0:
+                        if off == 0 or device in {'GW1NS-2'}:
                             bel.portmap[nam] = wire
                         else:
                             # not our cell, make an alias

examples/Makefile

@@ -19,7 +19,7 @@ all: attosoc-tec0117.fs nanolcd-tangnano.fs blinky-tec0117.fs blinky-runber.fs \
 	pll-52-tangnano.fs pll-80-tangnano.fs \
 	pll-54-tangnano1k.fs pll-81-tangnano1k.fs \
 	pll-dyn-tangnano.fs pll-dyn-tangnano1k.fs \
-	pll-tangnano4k.fs pll2-tangnano9k.fs pll2-tec0117.fs pll2-runber.fs \
+	pll-tangnano4k.fs pll2-tangnano9k.fs pll2-tec0117.fs pll2-runber.fs pll-dyn-honeycomb.fs \
 	pll-nanolcd-tangnano.fs pll-nanolcd-tangnano9k.fs
 
 unpacked: attosoc-tec0117-unpacked.v nanolcd-tangnano-unpacked.v blinky-tec0117-unpacked.v blinky-runber-unpacked.v \
@@ -39,7 +39,7 @@ unpacked: attosoc-tec0117-unpacked.v nanolcd-tangnano-unpacked.v blinky-tec0117-
 	pll-52-tangnano-unpacked.v pll-80-tangnano-unpacked.v \
 	pll-54-tangnano1k-unpacked.v pll-81-tangnano1k-unpacked.v \
 	pll-dyn-tangnano-unpacked.v pll-dyn-tangnano1k-unpacked.v \
-	pll2-tangnano9k-unpacked.v pll2-tec0117-unpacked.v pll2-runber-unpacked.v \
+	pll2-tangnano9k-unpacked.v pll2-tec0117-unpacked.v pll2-runber-unpacked.v pll-dyn-honeycomb-unpacked.v \
 	pll-nanolcd-tangnano-unpacked.v pll-nanolcd-tangnano9k-unpacked.v pll-tangnano4k-unpacked.v
 
 clean: 
@@ -96,7 +96,7 @@ pll-nanolcd-tangnano9k.fs: pll-nanolcd-tangnano9k.json
 	gowin_pack -d GW1NS-2 -o $@ $<
 
 %-honeycomb.json: %-honeycomb-synth.json honeycomb.cst
-	$(NEXTPNR) --json $< --write $@ --device GW1NS-UX2CQN48C5/I4 --cst honeycomb.cst
+	$(NEXTPNR) -v --debug --json $< --write $@ --device GW1NS-UX2CQN48C5/I4 --cst honeycomb.cst
 
 attosoc-tec0117-synth.json: attosoc/attosoc.v attosoc/picorv32.v
 	$(YOSYS) -p "read_verilog $^; synth_gowin -json $@"
@@ -155,6 +155,9 @@ pll-tangnano4k-synth.json: pll-tangnano4k.v pll/pllvr.v
 %-tangnano9k-synth.json: %.v
 	$(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@"
 
+pll-%-honeycomb-synth.json: pll/GW1NS-2C-%.vh pll.v pll/rpll.v
+	$(YOSYS) -D LEDS_NR=3 -D OSC_TYPE_OSCF -p "read_verilog $^; synth_gowin -json $@"
+
 %-honeycomb-synth.json: %.v
 	$(YOSYS) -D LEDS_NR=3 -D OSC_TYPE_OSCF -p "read_verilog $^; synth_gowin -json $@"
 

examples/pll.v

@@ -1,5 +1,8 @@
 `default_nettype none
-module top(input wire clk, input wire key, output wire [`LEDS_NR-1:0]led);
+`ifndef KEY
+	`define KEY key
+`endif
+module top(input wire clk, input wire KEY, output wire [`LEDS_NR-1:0]led);
 	wire VCC;
 	wire GND;
 	assign VCC = 1'b1;
@@ -44,7 +47,7 @@ module top(input wire clk, input wire key, output wire [`LEDS_NR-1:0]led);
     // dynamic
 `ifdef PLL_DYN
     always @ (posedge clk) begin
-        if (key) begin
+        if (KEY) begin
             fdiv <= ~`PLL_FBDIV_SEL;
             idiv <= ~`PLL_IDIV_SEL;
         end else begin
@@ -54,7 +57,7 @@ module top(input wire clk, input wire key, output wire [`LEDS_NR-1:0]led);
     end
 `else
 	always @ (posedge clk) begin
-		reset = ~key;
+		reset = ~KEY;
 	end
 `endif
 endmodule

examples/pll/GW1NS-2C-dyn.vh

@@ -0,0 +1,15 @@
+`define PLL_DYN
+`define PLL_DEVICE "GW1NS-2C"
+`define PLL_FCLKIN "24"
+`define PLL_ODIV_SEL  8
+
+`define PLL_FBDIV_SEL 12
+`define PLL_IDIV_SEL  5
+
+`define PLL_FBDIV_SEL_1 9
+`define PLL_IDIV_SEL_1  2
+
+`define PLL_FBDIV_SEL_LCD 29
+`define PLL_IDIV_SEL_LCD   7
+
+`define KEY rst