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The ODDR(c) element as part of the IOLOGIC
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Removed the old code specialized for ODDR(c), no longer creating
separate Bels for these primitives.

Slightly changed test example - now we use ODDRC primitive, which input
CLEAR is controlled by button - when pressed, primitive stops
functioning.

Signed-off-by: YRabbit <[email protected]>
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@yrabbit @pepijndevos
yrabbit authored and pepijndevos committed Apr 16, 2023
1 parent a2956e7 commit 9aede24
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Showing 6 changed files with 23 additions and 70 deletions.
9 changes: 0 additions & 9 deletions apycula/chipdb.py
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Original file line number Diff line number Diff line change
Expand Up @@ -912,8 +912,6 @@ def json_pinout(device):
else:
raise Exception("unsupported device")



_pll_inputs = [(5, 'CLKFB'), (6, 'FBDSEL0'), (7, 'FBDSEL1'), (8, 'FBDSEL2'), (9, 'FBDSEL3'),
(10, 'FBDSEL4'), (11, 'FBDSEL5'),
(12, 'IDSEL0'), (13, 'IDSEL1'), (14, 'IDSEL2'), (15, 'IDSEL3'), (16, 'IDSEL4'),
Expand Down Expand Up @@ -970,13 +968,6 @@ def dat_portmap(dat, dev, device):
bel.portmap['I'] = out
oe = wirenames[dat[f'Iobuf{pin}OE']]
bel.portmap['OE'] = oe
elif name.startswith("ODDR"):
d0 = wirenames[dat[f'Iologic{pin}In'][1]]
bel.portmap['D0'] = d0
d1 = wirenames[dat[f'Iologic{pin}In'][2]]
bel.portmap['D1'] = d1
tx = wirenames[dat[f'Iologic{pin}In'][27]]
bel.portmap['TX'] = tx
elif name.startswith("IOLOGIC"):
buf = name[-1]
for idx, nam in _iologic_inputs:
Expand Down
17 changes: 8 additions & 9 deletions apycula/gowin_pack.py
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Original file line number Diff line number Diff line change
Expand Up @@ -326,6 +326,8 @@ def set_pll_attrs(db, typ, idx, attrs):

_iologic_default_attrs = {
'DUMMY': {},
'ODDR': { 'TXCLK_POL': '0'},
'ODDRC': { 'TXCLK_POL': '0'},
'OSER4': { 'GSREN': 'false', 'LSREN': 'true', 'TXCLK_POL': '0', 'HWL': 'false'},
'OSER8': { 'GSREN': 'false', 'LSREN': 'true', 'TXCLK_POL': '0', 'HWL': 'false'},
'OSER10': { 'GSREN': 'false', 'LSREN': 'true'},
Expand Down Expand Up @@ -365,13 +367,17 @@ def set_iologic_attrs(db, attrs, param):
iologic_mod_attrs(in_attrs)
fin_attrs = set()
if 'OUTMODE' in attrs.keys():
in_attrs['CLKODDRMUX_WRCLK'] = 'ECLK0'
if attrs['OUTMODE'] != 'ODDRX1':
in_attrs['CLKODDRMUX_WRCLK'] = 'ECLK0'
if attrs['OUTMODE'] != 'ODDRX1' or param['IOLOGIC_TYPE'] == 'ODDRC':
in_attrs['LSROMUX_0'] = '1'
else:
in_attrs['LSROMUX_0'] = '0'
in_attrs['CLKODDRMUX_ECLK'] = 'UNKNOWN'
if param['IOLOGIC_FCLK'] in {'SPINE12', 'SPINE13'}:
in_attrs['CLKODDRMUX_ECLK'] = 'ECLK1'
elif param['IOLOGIC_FCLK'] in {'SPINE10', 'SPINE11'}:
in_attrs['CLKODDRMUX_ECLK'] = 'ECLK0'
in_attrs['LSROMUX_0'] = '1'
if attrs['OUTMODE'] == 'ODDRX8' or attrs['OUTMODE'] == 'DDRENABLE16':
in_attrs['LSROMUX_0'] = '0'
if attrs['OUTMODE'] == 'DDRENABLE16':
Expand Down Expand Up @@ -618,13 +624,6 @@ def place(db, tilemap, bels, cst, args):

if pinless_io:
return
elif typ == "ODDR":
bel = tiledata.bels[f'ODDR{num}']
bits = bel.modes['ENABLE'].copy()
if int(attrs["IOBUF"], 2):
bits.update(bel.flags['IOBUF'])
for r, c in bits:
tile[r][c] = 1
elif typ == "RAMW":
bel = tiledata.bels['RAM16']
bits = bel.modes['0']
Expand Down
13 changes: 10 additions & 3 deletions apycula/gowin_unpack.py
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Original file line number Diff line number Diff line change
Expand Up @@ -262,15 +262,20 @@ def parse_tile_(db, row, col, tile, default=True, noalias=False, noiostd = True)
continue
if 'OUTMODE' in attrvals.keys():
# XXX skip oddr
if attrvals['OUTMODE'] == attrids.iologic_attrvals['ODDRX1']:
if attrvals['OUTMODE'] == attrids.iologic_attrvals['MODDRX1']:
if 'LSROMUX_0' in attrvals.keys():
bels.setdefault(name, set()).add(f"MODE=ODDRC")
print(bels)
else:
bels.setdefault(name, set()).add(f"MODE=ODDR")
continue
# skip aux cells
if attrvals['OUTMODE'] == attrids.iologic_attrvals['DDRENABLE']:
continue
if attrids.iologic_num2val[attrvals['OUTMODE']] in _iologic_mode.keys():
bels.setdefault(name, set()).add(f"MODE={_iologic_mode[attrids.iologic_num2val[attrvals['OUTMODE']]]}")
elif 'INMODE' in attrvals.keys():
if attrvals['INMODE'] == attrids.iologic_attrvals['IDDRX1']:
if attrvals['INMODE'] == attrids.iologic_attrvals['MIDDRX1']:
if 'LSRIMUX_0' in attrvals.keys():
bels.setdefault(name, set()).add(f"MODE=IDDRC")
else:
Expand Down Expand Up @@ -599,6 +604,8 @@ def modify_pll_inputs(db, pll):
del pll.params['FBSEL']

_iologic_ports = {
'ODDR' : {'D0': 'D0', 'D1': 'D1', 'Q0': 'Q0', 'Q1': 'Q1', 'CLK': 'CLK'},
'ODDRC' : {'D0': 'D0', 'D1': 'D1', 'Q0': 'Q0', 'Q1': 'Q1', 'CLK': 'CLK', 'CLEAR': 'CLEAR'},
'OSER4': {'D0': 'D0', 'D1': 'D1', 'D2': 'D2', 'D3': 'D3',
'Q0': 'Q0', 'Q1': 'Q1', 'RESET': 'RESET', 'TX0': 'TX0',
'TX1': 'TX1', 'PCLK': 'PCLK', 'FCLK': 'FCLK'},
Expand Down Expand Up @@ -709,7 +716,7 @@ def tile2verilog(dbrow, dbcol, bels, pips, clock_pips, mod, cst, db):
name = f"R{row}C{col}_{iol_mode}_{idx}"
iol = mod.primitives.setdefault(name, codegen.Primitive(iol_mode, name))
iol.params.update(iol_params)
iol_oser = iol_mode in {'OSER4', 'OVIDEO', 'OSER8', 'OSER10', 'OSER16'}
iol_oser = iol_mode in {'ODDR', 'ODDRC', 'OSER4', 'OVIDEO', 'OSER8', 'OSER10', 'OSER16'}

portmap = db.grid[dbrow][dbcol].bels[bel].portmap
for port, wname in iologic_ports_by_type(iol_mode, portmap):
Expand Down
46 changes: 0 additions & 46 deletions apycula/tiled_fuzzer.py
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Original file line number Diff line number Diff line change
Expand Up @@ -602,51 +602,6 @@ def fse_diff_iob(fse, db, pin_locations, diff_cap_info):
# emulated LVDS
pass

# make IOLogic bels
_iologic_table = {'A' : 21, 'B' : 22}
_oddr_keys = {
'GW1N-1' : [[9, 0], [88, 0]],
'GW1NZ-1' : [[9, 0], [88, 0]],
'GW1NS-2' : [[10, 0], [90, 0]],
'GW1N-4' : [[9, 0], [88, 0]],
'GW1NS-4' : [[10, 0], [-39, 0], [91, 0]],
'GW1N-9' : [[10, 0], [91, 0]],
'GW1N-9C' : [[10, 0], [91, 0]],
}
_oddr_io_key = {89}
def fse_iologic(fse, db, pin_locations):
for ttyp, tiles in pin_locations.items():
pin_loc = list(tiles.keys())[0]
side, num = _tbrlre.match(pin_loc).groups()
row, col = tbrl2rc(fse, side, num)
bels = {name[-1] for loc in tiles.values() for name in loc}
for bel_idx in bels:
if bel_idx not in {'A', 'B'}:
continue
if 'shortval' in fse[ttyp] and _iologic_table[bel_idx] in fse[ttyp]['shortval']:
bel = db.grid[row][col].bels.setdefault(f"ODDR{bel_idx}", chipdb.Bel())
loc = set()
for fs in _oddr_keys[device] :
loc.update(get_shortval(fse, ttyp, _iologic_table[bel_idx], fs))
bel.modes.setdefault('ENABLE', loc)
# iobuf
# XXX not supporting T/IOBUF yet
#loc = get_longval(fse, ttyp, _pin_mode_longval[bel_idx],
# recode_key(_oddr_io_key))
#bel.flags.setdefault('IOBUF', loc)
bel.portmap = {
'D0': wirenames[dat[f'Iologic{bel_idx}In'][1]],
'D1': wirenames[dat[f'Iologic{bel_idx}In'][2]],
'CLK': wirenames[dat[f'Iologic{bel_idx}In'][17]],
'TX': wirenames[dat[f'Iologic{bel_idx}In'][27]],
}
# These two inputs are so far only found in the GW1N-9C,
# the purpose is not clear, but must be connected.
if dat[f'Iologic{bel_idx}In'][47] != -1:
bel.portmap.update({
'ODDR_ALWAYS_LOW': wirenames[dat[f'Iologic{bel_idx}In'][47]],
'ODDR_ALWAYS_HIGH': wirenames[dat[f'Iologic{bel_idx}In'][48]]
})

# IOB fuzzer
def find_next_loc(pin, locs):
Expand Down Expand Up @@ -1042,7 +997,6 @@ def run_pnr(mod, constr, config):
fse_slew_rate(fse, db, pin_locations)
fse_hysteresis(fse, db, pin_locations)
fse_drive(fse, db, pin_locations)
fse_iologic(fse, db, pin_locations)

# diff IOB
diff_cap_info = pindef.get_diff_cap_info(device, params['package'], True)
Expand Down
2 changes: 1 addition & 1 deletion examples/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ all: attosoc-tec0117.fs nanolcd-tangnano.fs blinky-tec0117.fs blinky-runber.fs \
tlvds-tangnano4k.fs tlvds-tangnano9k.fs tlvds-tec0117.fs \
tlvds-oddr-tangnano4k.fs tlvds-oddr-tangnano9k.fs tlvds-oddr-tec0117.fs \
blinky-oddr-tec0117.fs blinky-oddr-runber.fs \
blinky-oddr-tangnano.fs blinky-oddr-honeycomb.fs \
blinky-oddr-tangnano.fs blinky-oddr-tangnano1k.fs blinky-oddr-honeycomb.fs \
blinky-oddr-tangnano4k.fs blinky-oddr-tangnano9k.fs \
blinky-osc-tec0117.fs blinky-osc-runber.fs blinky-osc-tangnano.fs \
blinky-osc-honeycomb.fs \
Expand Down
6 changes: 4 additions & 2 deletions examples/blinky-oddr.v
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@
*/
module top (
input clk,
input key,
output [`LEDS_NR-1:0] led
);

Expand All @@ -18,13 +19,14 @@ assign ctr_d = ctr_q + 1'b1;
assign led[`LEDS_NR-1:2] = {(`LEDS_NR - 2){1'b1}};
assign led[0] = ctr_q[24:24];

ODDR oddr_0(
ODDRC oddr_0(
.D0(1'b0),
.D1(1'b1),
.CLK(ctr_q[24:24]),
.Q0(led[1]),
.Q1(),
.TX()
.TX(1'b1),
.CLEAR(!key)
);

endmodule

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