HCLK. Add delays

Optimistic delays for now, pending future revision. Signed-off-by: YRabbit <[email protected]>
YosysHQ · Sep 11, 2024 · af2975e · af2975e
1 parent 0964a8d
commit af2975e
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diff --git a/apycula/chipdb.py b/apycula/chipdb.py
@@ -3576,6 +3576,8 @@ def fse_wire_delays(db):
         db.wire_delay[clknames[i]] = "CENT_SPINE_PCLK"
     for i in range(129, 153): # clock inputs (logic->clock)
         db.wire_delay[clknames[i]] = "CENT_SPINE_PCLK"
+    for i in range(1000, 1010): # HCLK
+        db.wire_delay[clknames[i]] = "X0" # XXX
 
 # assign pads with plls
 # for now use static table and store the bel name although it is always PLL without a number

diff --git a/apycula/gowin_pack.py b/apycula/gowin_pack.py
@@ -2022,7 +2022,7 @@ def set_fuse():
         if side == 'L':
             col = 0
         else:
-            col = db.col - 1
+            col = db.cols - 1
         for row in range(db.rows):
             set_fuse()