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Change the IO coding to synthetic (#177)
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* Change the IO coding to synthetic

The new coding system uses a logicinfo table to search for the right
fuzes by given combinations of attributes.
Actually required bits are taken from vendor's longval tables.
The same tables are used to decode binary images.

tiled_fuzzer.py calls the vendor compiler only once to get an empty
image template.

* All references to IO coding bits, including standards, are removed from the base structure.
* Removed fuzzing IO.
* Removed fuzzing corner bank cells - their own table is used for them.
* Removed fuzzing of dual-purpose pins - their own table is used for them.
* Real LVDS primitives TLVDS_IBUF, TLVDS_TBUF and TLVDS_IOBUF are implemented.
* All emulated LVDS primitives are implemented: ELVDS_IBUF, ELVDS_OBUF,
  ELVDS_TBUF, ELVDS_IOBUF.
* All new primitives can connect with IOLOGIC.
* The OEN port of the I/O primitives (including differential ones) can
  be controlled by IOLOGIC.
* Added detection of gross user errors like placing TLVDS in place of
  the emulated one.
* It is possible to use as a differential special simplified IO elements
  located on the 6th row in the chips GW1N-1 and GW1NZ-1, but here may
  require additional research and in general the other pins should be
  enough.

Signed-off-by: YRabbit <[email protected]>

* Remove auxiliary function

It was used to minimize the bit representation of various I/O cell
features, but is no longer relevant due to the fact that bits are no
longer defined by fuzzing and are not stored in the database.

Signed-off-by: YRabbit <[email protected]>

---------

Signed-off-by: YRabbit <[email protected]>
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@yrabbit
yrabbit authored May 29, 2023
1 parent eebde52 commit d350cb7
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Showing 27 changed files with 752 additions and 1,128 deletions.
9 changes: 9 additions & 0 deletions apycula/attrids.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -625,6 +625,14 @@
# config
cfg_attrids = {
'GSR': 2,
'DONE_AS_GPIO': 4,
'JTAG_AS_GPIO': 6,
'READY_AS_GPIO': 7,
'MSPI_AS_GPIO': 8,
'RECONFIG_AS_GPIO': 9,
'SSPI_AS_GPIO': 10,
'I2C_AS_GPIO': 20,
'JTAG_EN': 21,
'POR': 24, # power on reset
}

Expand Down Expand Up @@ -793,4 +801,5 @@

# num -> attr name
iologic_num2val = {v: k for k, v in iologic_attrvals.items()}
iob_num2val = {v: k for k, v in iob_attrvals.items()}

86 changes: 9 additions & 77 deletions apycula/chipdb.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,41 +16,19 @@
# can be either tiles or bits within tiles
Coord = Tuple[int, int]

# IOB flag descriptor
# bitmask and possible values
@dataclass
class IOBFlag:
mask: Set[Coord] = field(default_factory = set)
options: Dict[str, Set[Coord]] = field(default_factory = dict)

# IOB mode descriptor
# bits and flags
# encode bits include all default flag values
@dataclass
class IOBMode:
encode_bits: Set[Coord] = field(default_factory = set)
decode_bits: Set[Coord] = field(default_factory = set)
flags: Dict[str, IOBFlag] = field(default_factory = dict)

@dataclass
class Bel:
"""Respresents a Basic ELement
with the specified modes mapped to bits
and the specified portmap"""
# there can be zero or more flags
flags: Dict[Union[int, str], Set[Coord]] = field(default_factory=dict)
# { iostd: { mode : IOBMode}}
iob_flags: Dict[str, Dict[str, IOBMode]] = field(default_factory=dict)
lvcmos121518_bits: Set[Coord] = field(default_factory = set)
# this Bel is IOBUF and needs routing to become IBUF or OBUF
simplified_iob: bool = field(default = False)
# differential signal capabilities info
is_diff: bool = field(default = False)
is_true_lvds: bool = field(default = False)
# banks
bank_mask: Set[Coord] = field(default_factory=set)
bank_flags: Dict[str, Set[Coord]] = field(default_factory=dict)
bank_input_only_modes: Dict[str, str] = field(default_factory=dict)
is_diff_p: bool = field(default = False)
# there can be only one mode, modes are exclusive
modes: Dict[Union[int, str], Set[Coord]] = field(default_factory=dict)
portmap: Dict[str, str] = field(default_factory=dict)
Expand Down Expand Up @@ -432,6 +410,7 @@ def set_banks(fse, db):
66: 'EFLASH',
68: 'ADC',
80: 'DLL1',
82: 'POWERSAVE',
}

def fse_fill_logic_tables(dev, fse):
Expand Down Expand Up @@ -771,7 +750,7 @@ def get_table_fuses(attrs, table):
have_full_key = True
for attrval in key:
if attrval == 0: # no "feature"
continue
break
if attrval > 0:
# this "feature" must present
if attrval not in attrs:
Expand All @@ -798,6 +777,12 @@ def get_shortval_fuses(dev, ttyp, attrs, table_name):
def get_longval_fuses(dev, ttyp, attrs, table_name):
return get_table_fuses(attrs, dev.longval[ttyp][table_name])

# get bank fuses
# The table for banks is different in that the first element in it is the
# number of the bank, thus allowing the repetition of elements in the key
def get_bank_fuses(dev, ttyp, attrs, table_name, bank_num):
return get_table_fuses(attrs, {k[1:]:val for k, val in dev.longval[ttyp][table_name].items() if k[0] == bank_num})

# add the attribute/value pair into an set, which is then passed to
# get_longval_fuses() and get_shortval_fuses()
def add_attr_val(dev, logic_table, attrs, attr, val):
Expand Down Expand Up @@ -1145,59 +1130,6 @@ def get_route_bits(db, row, col):
bits.update(v)
return bits

def diff2flag(dev):
""" Minimize bits for flag values and calc flag bitmask"""
seen_bels = []
for idx, row in enumerate(dev.grid):
for jdx, td in enumerate(row):
for name, bel in td.bels.items():
if name[0:3] == "IOB":
if not bel.iob_flags or bel in seen_bels:
continue
seen_bels.append(bel)
# get routing bits for cell
rbits = get_route_bits(dev, idx, jdx)
# If for a given mode all possible values of one flag
# contain some bit, then this bit is "noise" --- this bit
# belongs to the default value of another flag. Remove.
for iostd, iostd_rec in bel.iob_flags.items():
for mode, mode_rec in iostd_rec.items():
# if encoding has routing
r_encoding = mode_rec.encode_bits & rbits
mode_rec.encode_bits -= rbits
if r_encoding and mode != 'IOBUF':
bel.simplified_iob = True
mode_rec.decode_bits = mode_rec.encode_bits.copy()
for flag, flag_rec in mode_rec.flags.items():
noise_bits = None
for bits in flag_rec.options.values():
if noise_bits != None:
noise_bits &= bits
else:
noise_bits = bits.copy()
# remove noise
for bits in flag_rec.options.values():
bits -= noise_bits
flag_rec.mask |= bits
# decode bits don't include flags
for _, flag_rec in mode_rec.flags.items():
mode_rec.decode_bits -= flag_rec.mask
elif name[0:4] == "BANK":
noise_bits = None
for bits in bel.bank_flags.values():
if noise_bits != None:
noise_bits &= bits
else:
noise_bits = bits.copy()
mask = set()
for bits in bel.bank_flags.values():
bits -= noise_bits
mask |= bits
bel.bank_mask = mask
bel.modes['ENABLE'] -= mask
else:
continue

uturnlut = {'N': 'S', 'S': 'N', 'E': 'W', 'W': 'E'}
dirlut = {'N': (1, 0),
'E': (0, -1),
Expand Down
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