- a 5-stage-piplined 32-bit RISC V core built using the digital logic CAD simulator, see repo here.
- download all the files into one folder and open piplined_riscv_cpu.dig
- the cpu is currently confined to only these instructions: lw,sw,add,sub,and,or,slt,beq, addi, jal [more on the way]
- there is only one thing lefy which is to add a hazard unit (for handling pipline hazards)
- feel free to add your contribution if you find it helpful (: