GitHub - aedancullen/vlsi-cordic: Fixed-point CORDIC core in Verilog, with synthesis, PnR, and simulation

aedancullen / vlsi-cordic Public

Fixed-point CORDIC core in Verilog, with synthesis, PnR, and simulation

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Name		Name	Last commit message	Last commit date
Latest commit History 19 Commits
Encounter		Encounter
Irsim		Irsim
Modelsim		Modelsim
Modelsim_post_DC		Modelsim_post_DC
Padframe		Padframe
Synthesis		Synthesis
pinmap.pdf		pinmap.pdf
pinmap.png		pinmap.png
pinmap.svg		pinmap.svg
pinmap.txt		pinmap.txt
wiring.pdf		wiring.pdf
wiring.png		wiring.png
wiring.svg		wiring.svg