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Merge pull request chipsalliance#4019 from alainmarcel/alainmarcel-pa…
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…tch-1

Interface binding
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@alaindargelas
alaindargelas authored Dec 7, 2024
2 parents 100847c + 19dbece commit 298a9cd
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Showing 13 changed files with 1,982 additions and 1,535 deletions.
1 change: 1 addition & 0 deletions include/Surelog/Design/ModuleInstance.h
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Original file line number Diff line number Diff line change
Expand Up @@ -83,6 +83,7 @@ class ModuleInstance final : public ValuedComponentI {
}
}
ModuleInstance* getParent() const { return m_parent; }
void setParent(ModuleInstance* parent) { m_parent = parent; }
const FileContent* getFileContent() const { return m_fileContent; }
PathId getFileId() const;
NodeId getNodeId() const { return m_nodeId; }
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6 changes: 4 additions & 2 deletions src/DesignCompile/CompileFileContent.cpp
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Expand Up @@ -108,8 +108,10 @@ bool CompileFileContent::collectObjects_() {
break;
}
case VObjectType::paBind_directive: {
m_helper.compileBindStmt(m_fileContent, fC, id, m_compileDesign,
nullptr);
if (!m_declOnly) {
m_helper.compileBindStmt(m_fileContent, fC, id, m_compileDesign,
nullptr);
}
break;
}
case VObjectType::paParameter_declaration: {
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3 changes: 3 additions & 0 deletions src/DesignCompile/DesignElaboration.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -660,6 +660,9 @@ ModuleInstance* DesignElaboration::createBindInstance_(
if (instance) {
std::vector<ModuleInstance*> parentSubInstances;
instance->setInstanceBinding(parent);
if (instance->getParent() == nullptr) {
instance->setParent(parent);
}
NodeId parameterOverloading = fC->Sibling(bindNodeId);
if (fC->Type(parameterOverloading) ==
VObjectType::paHierarchical_instance) {
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798 changes: 27 additions & 771 deletions tests/AssertDelayError/AssertDelayError.log
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618 changes: 29 additions & 589 deletions tests/AssertTempError/AssertTempError.log
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197 changes: 128 additions & 69 deletions tests/BindStmt2/BindStmt2.log
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103 changes: 23 additions & 80 deletions tests/BindingPort/BindingPort.log
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Original file line number Diff line number Diff line change
Expand Up @@ -60,28 +60,28 @@ AST_DEBUG_END
[NTE:EL0503] ${SURELOG_DIR}/tests/BindingPort/dut.sv:4:1: Top level module "work@UART".
[ERR:EL0550] ${SURELOG_DIR}/tests/BindingPort/dut.sv:22:38: Unknown port "state".
[NTE:EL0508] Nb Top level modules: 1.
[NTE:EL0509] Max instance depth: 1.
[NTE:EL0510] Nb instances: 3.
[NTE:EL0511] Nb leaf instances: 2.
[NTE:EL0509] Max instance depth: 2.
[NTE:EL0510] Nb instances: 2.
[NTE:EL0511] Nb leaf instances: 1.
[INF:UH0706] Creating UHDM Model...
=== UHDM Object Stats Begin (Non-Elaborated Model) ===
design 1
logic_net 5
logic_typespec 8
module_inst 7
port 5
ref_obj 7
ref_typespec 8
logic_net 4
logic_typespec 6
module_inst 5
port 4
ref_obj 5
ref_typespec 6
=== UHDM Object Stats End ===
[INF:UH0707] Elaborating UHDM...
=== UHDM Object Stats Begin (Elaborated Model) ===
design 1
logic_net 5
logic_typespec 8
module_inst 7
port 8
ref_obj 12
ref_typespec 11
logic_net 4
logic_typespec 6
module_inst 5
port 6
ref_obj 8
ref_typespec 8
=== UHDM Object Stats End ===
[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/BindingPort/slpp_all/surelog.uhdm ...
[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/BindingPort/slpp_all/checker/surelog.chk.html ...
Expand Down Expand Up @@ -200,17 +200,18 @@ design: (work@UART)
|vpiInstance:
\_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10
|vpiModule:
\_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
\_module_inst: work@UART_assertions (work@UART.uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
|vpiParent:
\_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10
|vpiName:uut
|vpiFullName:[email protected]
|vpiDefName:work@UART_assertions
|vpiDefFile:${SURELOG_DIR}/tests/BindingPort/dut.sv
|vpiDefLineNo:13
|vpiNet:
\_logic_net: ([email protected]), line:14:11, endln:14:14
|vpiParent:
\_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
\_module_inst: work@UART_assertions (work@UART.uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
|vpiTypespec:
\_ref_typespec: ([email protected])
|vpiParent:
Expand All @@ -225,78 +226,24 @@ design: (work@UART)
|vpiPort:
\_port: (state), line:14:11, endln:14:14
|vpiParent:
\_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
\_module_inst: work@UART_assertions (work@UART.uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
|vpiName:state
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (work@UART.uut.state.clk), line:22:44, endln:22:47
\_ref_obj: ([email protected]), line:22:44, endln:22:47
|vpiParent:
\_port: (state), line:14:11, endln:14:14
|vpiName:clk
|vpiFullName:work@UART.uut.state.clk
|vpiFullName:[email protected]
|vpiActual:
\_logic_net: ([email protected]), line:14:11, endln:14:14
|vpiLowConn:
\_ref_obj: (uut.clk), line:22:38, endln:22:43
\_ref_obj: (work@UART.uut.clk), line:22:38, endln:22:43
|vpiParent:
\_port: (state), line:14:11, endln:14:14
|vpiName:clk
|vpiFullName:uut.clk
|vpiActual:
\_logic_net: ([email protected]), line:14:11, endln:14:14
|vpiTypedef:
\_ref_typespec: ([email protected])
|vpiParent:
\_port: (state), line:14:11, endln:14:14
|vpiFullName:[email protected]
|vpiActual:
\_logic_typespec: , line:14:11, endln:14:11
|vpiInstance:
\_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
|vpiModule:
\_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
|vpiParent:
\_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10
|vpiName:uut
|vpiDefName:work@UART_assertions
|vpiDefFile:${SURELOG_DIR}/tests/BindingPort/dut.sv
|vpiDefLineNo:13
|vpiNet:
\_logic_net: ([email protected]), line:14:11, endln:14:14
|vpiParent:
\_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
|vpiTypespec:
\_ref_typespec: ([email protected])
|vpiParent:
\_logic_net: ([email protected]), line:14:11, endln:14:14
|vpiFullName:[email protected]
|vpiActual:
\_logic_typespec: , line:14:11, endln:14:11
|vpiName:clk
|vpiFullName:[email protected]
|vpiInstance:
\_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10
|vpiPort:
\_port: (state), line:14:11, endln:14:14
|vpiParent:
\_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
|vpiName:state
|vpiDirection:1
|vpiHighConn:
\_ref_obj: ([email protected]), line:22:44, endln:22:47
|vpiParent:
\_port: (state), line:14:11, endln:14:14
|vpiName:clk
|vpiFullName:[email protected]
|vpiActual:
\_logic_net: ([email protected]), line:14:11, endln:14:14
|vpiLowConn:
\_ref_obj: (uut.clk), line:22:38, endln:22:43
|vpiParent:
\_port: (state), line:14:11, endln:14:14
|vpiName:clk
|vpiFullName:uut.clk
|vpiActual:
\_logic_net: ([email protected]), line:14:11, endln:14:14
|vpiTypedef:
\_ref_typespec: ([email protected])
Expand All @@ -306,17 +253,13 @@ design: (work@UART)
|vpiActual:
\_logic_typespec: , line:14:11, endln:14:11
|vpiInstance:
\_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
\_module_inst: work@UART_assertions (work@UART.uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
\_weaklyReferenced:
\_logic_typespec: , line:5:11, endln:5:11
\_logic_typespec: , line:5:11, endln:5:11
|vpiParent:
\_logic_net: ([email protected]), line:5:11, endln:5:14
\_logic_typespec: , line:14:11, endln:14:11
\_logic_typespec: , line:14:11, endln:14:11
|vpiParent:
\_logic_net: ([email protected]), line:14:11, endln:14:14
\_logic_typespec: , line:14:11, endln:14:11
\_logic_typespec: , line:14:11, endln:14:11
|vpiParent:
\_logic_net: ([email protected]), line:14:11, endln:14:14
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