RISCV_LBIST

HW assignment of Testing and Fault Tolerance course, BIST module for RiscV core.

Dirs

bist folder
core rtl
synthesis scripts
core rtl tbs
tmp scripts

Usage

scan chains insertion script starting from synthesized netlist insert scan chains and generate a dft netlist and the relative STIL procedure (for TMAX script)
synthesis script
TMAX script for fault testing purposes.

Project description

The purpose of this project is to design a Logic-BIST for testing a RISCV core trough the adoption of some testing techniques presented during the course (Here is presented an example of the Test-per-scan technique, with some differences) and usage of industrial tools (TetraMax, Modelsim, DesignCompiler). The constraints in terms of test coverage, are at least 70% of coverage for the Stuck-At fault model

Further information

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