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Fix AXI_ADDR_BIT_OFFSET and AXIL_ADDR_BIT_OFFSET part select #49

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Fix AXI_ADDR_BIT_OFFSET and AXIL_ADDR_BIT_OFFSET part select #49

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c4e502d
Workaround AXI_ADDR_BIT_OFFSET and AXIL_ADDR_BIT_OFFSET part select
AlexLao512 Mar 5, 2023
38dea12
Workaround AXI_ADDR_BIT_OFFSET and AXIL_ADDR_BIT_OFFSET error in Mode…
AlexLao512 Mar 10, 2023
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8 changes: 4 additions & 4 deletions rtl/axi_axil_adapter_rd.v
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Original file line number Diff line number Diff line change
Expand Up @@ -286,7 +286,7 @@ always @* begin

if (m_axil_rready && m_axil_rvalid) begin
s_axi_rid_next = id_reg;
s_axi_rdata_next = m_axil_rdata >> (addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH);
s_axi_rdata_next = m_axil_rdata >> (addr_reg[AXIL_ADDR_BIT_OFFSET-1 -: AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH);
s_axi_rresp_next = m_axil_rresp;
s_axi_rlast_next = 1'b0;
s_axi_rvalid_next = 1'b1;
Expand Down Expand Up @@ -316,7 +316,7 @@ always @* begin
s_axi_rid_next = id_reg;
data_next = m_axil_rdata;
resp_next = m_axil_rresp;
s_axi_rdata_next = m_axil_rdata >> (addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH);
s_axi_rdata_next = m_axil_rdata >> (addr_reg[AXIL_ADDR_BIT_OFFSET-1 -: AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH);
s_axi_rresp_next = m_axil_rresp;
s_axi_rlast_next = 1'b0;
s_axi_rvalid_next = 1'b1;
Expand Down Expand Up @@ -346,7 +346,7 @@ always @* begin

if (s_axi_rready || !s_axi_rvalid) begin
s_axi_rid_next = id_reg;
s_axi_rdata_next = data_reg >> (addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH);
s_axi_rdata_next = data_reg >> (addr_reg[AXIL_ADDR_BIT_OFFSET-1 -: AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH);
s_axi_rresp_next = resp_reg;
s_axi_rlast_next = 1'b0;
s_axi_rvalid_next = 1'b1;
Expand Down Expand Up @@ -412,7 +412,7 @@ always @* begin
m_axil_rready_next = !s_axi_rvalid && !m_axil_arvalid;

if (m_axil_rready && m_axil_rvalid) begin
data_next[addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = m_axil_rdata;
data_next[addr_reg[AXI_ADDR_BIT_OFFSET-1 -: AXIL_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = m_axil_rdata;
if (m_axil_rresp) begin
resp_next = m_axil_rresp;
end
Expand Down
18 changes: 9 additions & 9 deletions rtl/axi_axil_adapter_wr.v
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Original file line number Diff line number Diff line change
Expand Up @@ -335,7 +335,7 @@ always @* begin

if (s_axi_wready && s_axi_wvalid) begin
m_axil_wdata_next = {(AXIL_WORD_WIDTH/AXI_WORD_WIDTH){s_axi_wdata}};
m_axil_wstrb_next = s_axi_wstrb << (addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_STRB_WIDTH);
m_axil_wstrb_next = s_axi_wstrb << (addr_reg[AXIL_ADDR_BIT_OFFSET-1 -: AXI_ADDR_BIT_OFFSET] * AXI_STRB_WIDTH);
m_axil_wvalid_next = 1'b1;
burst_next = burst_reg - 1;
burst_active_next = burst_reg != 0;
Expand All @@ -354,13 +354,13 @@ always @* begin
if (CONVERT_NARROW_BURST) begin
for (i = 0; i < AXI_WORD_WIDTH; i = i + 1) begin
if (s_axi_wstrb[i]) begin
data_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH+i*AXIL_WORD_SIZE +: AXIL_WORD_SIZE] = s_axi_wdata[i*AXIL_WORD_SIZE +: AXIL_WORD_SIZE];
strb_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET]*SEGMENT_STRB_WIDTH+i] = 1'b1;
data_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1 -: AXI_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH+i*AXIL_WORD_SIZE +: AXIL_WORD_SIZE] = s_axi_wdata[i*AXIL_WORD_SIZE +: AXIL_WORD_SIZE];
strb_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1 -: AXI_ADDR_BIT_OFFSET]*SEGMENT_STRB_WIDTH+i] = 1'b1;
end
end
end else begin
data_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = s_axi_wdata;
strb_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET]*SEGMENT_STRB_WIDTH +: SEGMENT_STRB_WIDTH] = s_axi_wstrb;
data_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1 -: AXI_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = s_axi_wdata;
strb_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1 -: AXI_ADDR_BIT_OFFSET]*SEGMENT_STRB_WIDTH +: SEGMENT_STRB_WIDTH] = s_axi_wstrb;
end
m_axil_wdata_next = data_next;
m_axil_wstrb_next = strb_next;
Expand Down Expand Up @@ -451,8 +451,8 @@ always @* begin
if (s_axi_wready && s_axi_wvalid) begin
data_next = s_axi_wdata;
strb_next = s_axi_wstrb;
m_axil_wdata_next = s_axi_wdata >> (addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_DATA_WIDTH);
m_axil_wstrb_next = s_axi_wstrb >> (addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_STRB_WIDTH);
m_axil_wdata_next = s_axi_wdata >> (addr_reg[AXI_ADDR_BIT_OFFSET-1 -: AXIL_ADDR_BIT_OFFSET] * AXIL_DATA_WIDTH);
m_axil_wstrb_next = s_axi_wstrb >> (addr_reg[AXI_ADDR_BIT_OFFSET-1 -: AXIL_ADDR_BIT_OFFSET] * AXIL_STRB_WIDTH);
m_axil_wvalid_next = 1'b1;
burst_next = burst_reg - 1;
burst_active_next = burst_reg != 0;
Expand All @@ -469,8 +469,8 @@ always @* begin
s_axi_wready_next = 1'b0;

if (!m_axil_wvalid || m_axil_wready) begin
m_axil_wdata_next = data_reg >> (addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_DATA_WIDTH);
m_axil_wstrb_next = strb_reg >> (addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_STRB_WIDTH);
m_axil_wdata_next = data_reg >> (addr_reg[AXI_ADDR_BIT_OFFSET-1 -: AXIL_ADDR_BIT_OFFSET] * AXIL_DATA_WIDTH);
m_axil_wstrb_next = strb_reg >> (addr_reg[AXI_ADDR_BIT_OFFSET-1 -: AXIL_ADDR_BIT_OFFSET] * AXIL_STRB_WIDTH);
m_axil_wvalid_next = 1'b1;
addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_WIDTH{1'b1}} << master_burst_size_reg);
last_segment_next = addr_next[burst_size_reg] != addr_reg[burst_size_reg];
Expand Down