ttl/sn74280: Implement

ttl/sn74280.vhd

@@ -14,5 +14,11 @@ end;
 
 architecture ttl of sn74280 is
 begin
-
+  process (i0, i1, i2, i3, i4, i5, i6, i7, i8)
+    variable parity : std_logic;
+  begin
+    parity := i0 xor i1 xor i2 xor i3 xor i4 xor i5 xor i6 xor i7 xor i8;
+    even <= not parity;
+    odd <= parity;
+  end process;
 end;

ttl/sn74280_tb.vhd

@@ -38,11 +38,35 @@ begin
     );
 
   process
-  begin
-    wait for 5 ns;
+    type test_vec is record
+      i0, i1, i2, i3, i4, i5, i6, i7, i8: std_logic;
+      e, o: std_logic;
+    end record;
+    type test_vecs is array (natural range <>) of test_vec;
 
-    report "Testbench not implemented!" severity warning;
+    constant tests : test_vecs :=
+      (('0', '0', '0', '0', '0', '0', '0', '0', '0', '1', '0'),
+       ('1', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1'),
+       ('1', '0', '1', '0', '1', '0', '1', '0', '0', '1', '0'),
+       ('1', '1', '1', '1', '1', '0', '1', '0', '0', '1', '0'),
+       ('1', '0', '1', '1', '1', '0', '1', '0', '0', '0', '1'),
+       ('1', '1', '1', '1', '1', '1', '1', '1', '1', '0', '1'));
 
+  begin
+    for i in tests'range loop
+      i0 <= tests(i).i0;
+      i1 <= tests(i).i1;
+      i2 <= tests(i).i2;
+      i3 <= tests(i).i3;
+      i4 <= tests(i).i4;
+      i5 <= tests(i).i5;
+      i6 <= tests(i).i6;
+      i7 <= tests(i).i7;
+      i8 <= tests(i).i8;
+      wait for 5 ns;
+      assert even = tests(i).e report "failure in case: " & integer'image(i);
+      assert odd = tests(i).o report "failure in case: " & integer'image(i);
+    end loop;
     wait;
   end process;