Merge pull request #12 from alex-segura/ttl/sn74153

ttl/sn74153: Implement

TODO.org

@@ -1,6 +1,6 @@
 TODO List for the CADR4 project
 
-* TODO TTLs [17/59]
+* TODO TTLs [18/59]
 
 Header template for files:
 
@@ -415,15 +415,15 @@ Header template for files:
  - [X] Implement component
  - [X] Implement skeleton testbench
  - [X] Implement rudimentary testbench
-** TODO sn74s153 (DUAL 4-1 SELECT) [3/5]
+** DONE sn74s153 (DUAL 4-1 SELECT) [5/5]
  - [X] Store datasheet and upstream URL.
 	https://www.ti.com/lit/ds/symlink/sn74ls153.pdf
  - [X] Implement skeleton component.
    All components should have on the first line a single line
    description of the component.
- - [ ] Implement component
+ - [X] Implement component
  - [X] Implement skeleton testbench
- - [ ] Implement rudimentary testbench
+ - [X] Implement rudimentary testbench
 ** TODO sn74s181 (ALU) [3/5]
  - [X] Store datasheet and upstream URL.
 	https://www.ti.com/lit/ds/symlink/sn54ls181.pdf

ttl/sn74153.vhd

@@ -23,5 +23,32 @@ end;
 
 architecture ttl of sn74153 is
 begin
-
+  process (enb1_n, sel0, g1c0, g1c1, g1c2, g1c3,
+           enb2_n, sel1, g2c0, g2c1, g2c2, g2c3)
+    variable sel: std_logic_vector(0 to 1);
+  begin
+    sel := sel1 & sel0;
+    if enb1_n then
+      g1q <= '0';
+    else
+      case sel is
+        when "00" => g1q <= g1c0;
+        when "01" => g1q <= g1c1;
+        when "10" => g1q <= g1c2;
+        when "11" => g1q <= g1c3;
+        when others => g1q <= 'X';
+      end case;
+    end if;
+    if enb2_n then
+      g2q <= '0';
+    else
+      case sel is
+        when "00" => g2q <= g2c0;
+        when "01" => g2q <= g2c1;
+        when "10" => g2q <= g2c2;
+        when "11" => g2q <= g2c3;
+        when others => g2q <= 'X';
+      end case;
+    end if;
+end process;
 end;

ttl/sn74153_tb.vhd

@@ -44,10 +44,71 @@ begin
     );
 
   process
+    type test_vec is record
+      c0, c1, c2, c3: std_logic;
+      b, a: std_logic;
+      o: std_logic;
+    end record;
+    type test_vecs is array (natural range <>) of test_vec;
+
+    constant tests : test_vecs :=
+      (('0', '1', '1', '1', '0', '0', '0'),
+       ('1', '1', '1', '1', '0', '0', '1'),
+       ('1', '0', '1', '1', '0', '1', '0'),
+       ('1', '1', '1', '1', '0', '1', '1'),
+       ('1', '1', '0', '1', '1', '0', '0'),
+       ('1', '1', '1', '1', '1', '0', '1'),
+       ('1', '1', '1', '0', '1', '1', '0'),
+       ('1', '1', '1', '1', '1', '1', '1'));
+
   begin
-    wait for 5 ns;
+    for i in tests'range loop
+      g1c0 <= tests(i).c0;
+      g1c1 <= tests(i).c1;
+      g1c2 <= tests(i).c2;
+      g1c3 <= tests(i).c3;
+      sel1 <= tests(i).b;
+      sel0 <= tests(i).a;
+      enb1_n <= '1';
+      wait for 5 ns;
+      assert g1q = '0' report "strobe 1 failure case: " & integer'image(i);
+    end loop;
+
+    for i in tests'range loop
+      g2c0 <= tests(i).c0;
+      g2c1 <= tests(i).c1;
+      g2c2 <= tests(i).c2;
+      g2c3 <= tests(i).c3;
+      sel1 <= tests(i).b;
+      sel0 <= tests(i).a;
+      enb2_n <= '1';
+      wait for 5 ns;
+      assert g2q = '0' report "strobe 2 failure case: " & integer'image(i);
+    end loop;
+
+    for i in tests'range loop
+      enb1_n <= '0';
+      g1c0 <= tests(i).c0;
+      g1c1 <= tests(i).c1;
+      g1c2 <= tests(i).c2;
+      g1c3 <= tests(i).c3;
+      sel1 <= tests(i).b;
+      sel0 <= tests(i).a;
+      wait for 5 ns;
+      assert g1q = tests(i).o report "sel 1 failure case: " & integer'image(i);
+    end loop;
 
-    report "Testbench not implemented!" severity warning;
+    for i in tests'range loop
+      enb2_n <= '0';
+      g2c0 <= tests(i).c0;
+      g2c1 <= tests(i).c1;
+      g2c2 <= tests(i).c2;
+      g2c3 <= tests(i).c3;
+      sel1 <= tests(i).b;
+      sel0 <= tests(i).a;
+      wait for 5 ns;
+      assert g2q = tests(i).o report "sel 2 failure case: " & integer'image(i);
+    end loop;
 
     wait;
   end process;