Merge pull request efabless#28 from Manarabdelaty/incr_user_ram_blocks

Updated default number of sram blocks for the user area
antmicro · Nov 2, 2020 · c13de45 · c13de45
2 parents d855783 + ff52415
commit c13de45
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Showing 4 changed files with 7 additions and 3 deletions.
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v
@@ -11,4 +11,4 @@
 
 // Number of RAM blocks for the mgmt_core
 `define MGMT_BLOCKS 2
-`define USER_BLOCKS 4
+`define USER_BLOCKS 6
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
@@ -220,6 +220,8 @@ module mgmt_soc (
     };
 
     parameter [(`USER_BLOCKS*24)-1:0] USER_BLOCKS_ADR = {
+        {24'h 50_0000}, 
+        {24'h 40_0000},
         {24'h 30_0000},
         {24'h 20_0000},
         {24'h 10_0000},

diff --git a/verilog/rtl/storage.v b/verilog/rtl/storage.v
@@ -3,7 +3,7 @@
    Management area has R/W access for MGMT_BLOCKS and RO access for USER_BLOCKS */
 
 module storage #(
-    parameter USER_BLOCKS = 4,  // R/W access
+    parameter USER_BLOCKS = 6,  // R/W access
     parameter MGMT_BLOCKS = 2   // R/W access
 ) (
     // MGMT_AREA R/W Interface (MGMT_BLOCKS)

diff --git a/verilog/rtl/storage_bridge_wb.v b/verilog/rtl/storage_bridge_wb.v
@@ -1,5 +1,5 @@
 module storage_bridge_wb #(
-    parameter USER_BLOCKS = 4, 
+    parameter USER_BLOCKS = 6, 
     parameter MGMT_BLOCKS = 2,
     parameter MGMT_BASE_ADR = 32'h 0100_0000,
     parameter USER_BASE_ADR = 32'h 0200_0000
@@ -40,6 +40,8 @@ module storage_bridge_wb #(
     };
 
     parameter [(USER_BLOCKS*24)-1:0] USER_BLOCKS_ADR = {
+        {24'h 50_0000},
+        {24'h 40_0000},
         {24'h 30_0000},
         {24'h 20_0000},
         {24'h 10_0000},