[#65950] docs tooltips

docs/requirements.txt

@@ -1,2 +1,3 @@
 -r ../requirements.txt
 https://github.com/antmicro/antmicro-sphinx-utils/archive/main.zip
+sphinx-tippy

docs/source/conf.py

@@ -29,104 +29,107 @@
     extensions as default_extensions,
     myst_enable_extensions as default_myst_enable_extensions,
     antmicro_html,
-    antmicro_latex
+    antmicro_latex,
 )
 
 # -- General configuration -----------------------------------------------------
 
 # General information about the project.
-project = u'Rowhammer tester'
-basic_filename = u'rowhammer-tester'
-if 'tags' in globals() and 'internal' in tags:
-    basic_filename = 'INTERNAL--' + basic_filename
-authors = u'Antmicro'
-copyright = authors + u', 2021-2023'
+project = "Rowhammer tester"
+basic_filename = "rowhammer-tester"
+if "tags" in globals() and "internal" in tags:
+    basic_filename = "INTERNAL--" + basic_filename
+authors = "Antmicro"
+copyright = authors + ", 2021-2023"
 
 # The short X.Y version.
-version = ''
+version = ""
 # The full version, including alpha/beta/rc tags.
-release = ''
+release = ""
 
 # This is temporary before the clash between myst-parser and immaterial is fixed
 sphinx_immaterial_override_builtin_admonitions = False
 
 numfig = True
 
-extensions = list(set(default_extensions + [
-    'sphinx_tabs.tabs',
-    'sphinx.ext.autosectionlabel',
-    'sphinxcontrib.wavedrom',
-]))
+extensions = list(
+    set(
+        default_extensions
+        + [
+            "sphinx_tabs.tabs",
+            "sphinx.ext.autosectionlabel",
+            "sphinxcontrib.wavedrom",
+            "sphinx_tippy",
+        ]
+    )
+)
 
 # Supress duplicate label warnings from autosectionlabel
-suppress_warnings = ['autosectionlabel.*']
+suppress_warnings = ["autosectionlabel.*"]
 
 myst_enable_extensions = default_myst_enable_extensions
 
-myst_substitutions = {
-    "project": project
-}
+myst_substitutions = {"project": project}
 
-today_fmt = '%Y-%m-%d'
+today_fmt = "%Y-%m-%d"
 
-todo_include_todos=False
+todo_include_todos = False
 
 # -- Options for HTML output ---------------------------------------------------
 
-html_theme = 'sphinx_immaterial'
+html_theme = "sphinx_immaterial"
 
 html_last_updated_fmt = today_fmt
 
 html_show_sphinx = False
 
 html_title = project
 
-(
-    html_logo,
-    html_theme_options,
-    html_context
-) = antmicro_html(
-    gh_slug="antmicro/rowhammer-tester",
-    pdf_url=f"{basic_filename}.pdf"
+(html_logo, html_theme_options, html_context) = antmicro_html(
+    gh_slug="antmicro/rowhammer-tester", pdf_url=f"{basic_filename}.pdf"
 )
 
 render_using_wavedrompy = True
 
 offline_wavedrom_js_path = r"WaveDrom.js"
-offline_skin_js_path =  r"default.js"
+offline_skin_js_path = r"default.js"
 
 html_show_sourcelink = True
 html_sidebars = {
     "**": ["logo-text.html", "globaltoc.html", "localtoc.html", "searchbox.html"]
 }
 
-html_static_path = ['build/arty/documentation/_static/']
-
-for target in ['arty', 'zcu104', 'ddr4_datacenter_test_board',
-    'lpddr4_test_board', 'ddr5_test_board','ddr5_tester']:
-    run([
-        'python3',
-        f'../../rowhammer_tester/targets/{target}.py',
-        '--docs',
-    ])
-    run([
-        'cp',
-        f'images/{target}_CRG.png',
-        f'build/{target}/documentation/{target}_CRG.png',
-    ])
+html_static_path = ["build/arty/documentation/_static/"]
+
+for target in [
+    "arty",
+    "zcu104",
+    "ddr4_datacenter_test_board",
+    "lpddr4_test_board",
+    "ddr5_test_board",
+    "ddr5_tester",
+]:
+    run(
+        [
+            "python3",
+            f"../../rowhammer_tester/targets/{target}.py",
+            "--docs",
+        ]
+    )
+    run(
+        [
+            "cp",
+            f"images/{target}_CRG.png",
+            f"build/{target}/documentation/{target}_CRG.png",
+        ]
+    )
 
 # -- Options for LaTeX output --------------------------------------------------
 
-(
-    latex_elements,
-    latex_documents,
-    latex_logo,
-    latex_additional_files
-) = antmicro_latex(basic_filename, project, authors)
+(latex_elements, latex_documents, latex_logo, latex_additional_files) = antmicro_latex(
+    basic_filename, project, authors
+)
 
 # -- Options for man output ----------------------------------------------------
 
-man_pages = [
-    ('index', basic_filename, project,
-     [authors], 1)
-]
+man_pages = [("index", basic_filename, project, [authors], 1)]

docs/source/ddr4_datacenter_dram_tester.md

@@ -1,9 +1,9 @@
-# Data Center DRAM Tester
+# Data Center RDIMM DDR4 Tester
 
-```{image} images/ddr4_datacenter_dram_tester.jpg
+```{image} images/data-center-rdimm-ddr4-tester-1.2.0.png
 ```
 
-The data center DRAM tester is an open source hardware test platform that enables testing and experimenting with various DDR4 RDIMMs (Registered Dual In-Line Memory Module).
+The Data Center RDIMM DDR4 Tester is an open source hardware test platform that enables testing and experimenting with various DDR4 RDIMMs (Registered Dual In-Line Memory Module).
 
 The hardware is open and can be found on GitHub:
 <https://github.com/antmicro/data-center-dram-tester/>
@@ -12,7 +12,11 @@ The following instructions explain how to set up the board.
 
 ## Board configuration
 
-First connect the board USB and Ethernet cables to your computer, plug the board to the socket and turn it on using power switch. Then configure the network. The board's IP address will be `192.168.100.50` (so you could e.g. use `192.168.100.2/24`). The `IP_ADDRESS` environment variable can be used to modify the board's address.
+Connect power supply (7-15VDC) to [`J3`](#data-center-dram-tester_J3) barrel jack. Then connect the board USB cable ([`J9`](#data-center-dram-tester_J9)) and Ethernet cable ([`J2`](#data-center-dram-tester_J2)) to your computer and insert the memory module to the socket [`U14`](#data-center-dram-tester_U14).
+To turn the board on, use power switch [`S3`](#data-center-dram-tester_S3). 
+
+After power is up, configure the network. The board's IP address will be `192.168.100.50` (so you could e.g. use `192.168.100.2/24`). The `IP_ADDRESS` environment variable can be used to modify the board's address.
+
 Next, generate the FPGA bitstream:
 
 ```sh
@@ -38,9 +42,4 @@ export TARGET=ddr4_datacenter_test_board
 make flash
 ```
 
-```{warning}
-There is a JTAG/SPI jumper named `MODE2` on the right side of the board.
-Unless it's set to the SPI setting, the FPGA will load the bitstream received via JTAG.
-```
-
-Bitstream will be loaded from flash memory upon device power-on or after a PROG button press.
+Bitstream will be loaded from flash memory upon device power-on or after a [`PROG_B1`](#data-center-dram-tester_PROG_B1) button press.

docs/source/ddr5_test_board.md

@@ -1,4 +1,4 @@
-# DDR5 Test Board
+# LPDDR4 Test Board with DDR5 Testbed
 
 ```{image} images/lpddr4-test-board.jpg
 ```
@@ -15,7 +15,10 @@ The following instructions explain how to set up the board.
 
 ## Board configuration
 
-First connect the board USB and Ethernet cables to your computer, plug the board to the socket and turn it on using power switch. Then configure the network. The board's IP address will be `192.168.100.50` (so you could e.g. use `192.168.100.2/24`). The `IP_ADDRESS` environment variable can be used to modify the board's address.
+Connect power supply (7-15VDC) to [`J6`](#lpddr4-test-board_J6) barrel jack.
+Then connect the board's USB-C [`J1`](#lpddr4-test-board_J1) and Ethernet [`J5`](#lpddr4-test-board_J5) interfaces to your computer.
+Turn the board on using power switch [`S1`](#lpddr4-test-board_S1).
+Then configure the network. The board's IP address will be `192.168.100.50` (so you could e.g. use `192.168.100.2/24`). The `IP_ADDRESS` environment variable can be used to modify the board's address.
 Next, generate the FPGA bitstream:
 
 ```sh
@@ -48,8 +51,8 @@ make flash
 ```
 
 ```{warning}
-There is a JTAG/SPI jumper named `MODE2` on the right side of the board.
-Unless it's set to the SPI setting, the FPGA will load the bitstream received via JTAG.
+There is a JTAG/FLASH jumper [`MODE1`](#lpddr4-test-board_MODE1) on the right side of the board.
+Unless it's set to the FLASH setting, the FPGA will load the bitstream received via JTAG ([`J4`](#lpddr4-test-board_J4)).
 ```
 
-Bitstream will be loaded from flash memory upon device power-on or after a PROG button press.
+Bitstream will be loaded from flash memory upon device power-on or after a PROG button ([`PROG_B1`](#lpddr4-test-board_PROG_B1)) press.

docs/source/ddr5_tester.md

@@ -1,9 +1,9 @@
-# DDR5 Tester
+# Data Center RDIMM DDR5 Tester
 
 ```{image} images/datacenter-rdimm-ddr5-tester.png
 ```
 
-The DDR5 tester is an open source hardware test platform that enables testing and experimenting with various DDR5 RDIMMs (Registered Dual In-Line Memory Module).
+The Data Center RDIMM DDR5 Tester is an open source hardware test platform that enables testing and experimenting with various DDR5 RDIMMs (Registered Dual In-Line Memory Module).
 
 The hardware is open and can be found on GitHub:
 <https://github.com/antmicro/ddr5-tester/>
@@ -12,7 +12,9 @@ The following instructions explain how to set up the board.
 
 ## Rowhammer Tester Target Configuration
 
-First connect the board USB and Ethernet cables to your computer, plug the board to the socket and turn it on using power switch. Then configure the network. The board's IP address will be `192.168.100.50` (so you could e.g. use `192.168.100.2/24`). The `IP_ADDRESS` environment variable can be used to modify the board's address.
+Connect power supply (12-15VDC) to [`J1`](#ddr5-tester_J1) barrel jack. Then connect the board USB cable ([`J6`](#ddr5-tester_J6)) and Ethernet cable ([`J4`](#ddr5-tester_J4)) to your computer and insert the memory module to the socket [`U12`](#ddr5-tester_U12).
+To turn the board on, use power switch [`S1`](#ddr5-tester_S1). 
+After power is up, configure the network. The board's IP address will be `192.168.100.50` (so you could e.g. use `192.168.100.2/24`). The `IP_ADDRESS` environment variable can be used to modify the board's address.
 Next, generate the FPGA bitstream:
 
 ```sh
@@ -45,15 +47,15 @@ make flash
 ```
 
 ```{warning}
-There is a JTAG/SPI jumper named `MODE` on the right side of the board.
-Unless it's set to the SPI setting, the FPGA will load the bitstream received via JTAG.
+There is a JTAG/SPI switch ([`MODE1`](#ddr5-tester_MODE1)) on the right side of the board.
+Unless it's set to the SPI setting, the FPGA will load the bitstream received via JTAG ([`J3`](#ddr5-tester_J3)).
 ```
 
-Bitstream will be loaded from flash memory upon device power-on or after a PROG button press.
+Bitstream will be loaded from flash memory upon device power-on or after a [`PROG_B1`](#ddr5-tester_PROG_B1) button press.
 
 ## Linux Target Configuration
 
-There's another DDR5 Tester tagret provided.
+There's another RDIMM DDR5 Tester tagret provided.
 The `ddr5_tester_linux` is a linux capable target (**with no rowhammer tester**) that allows you to define custom DDR5 tester module utilizing linux-based software.
 
 ### Base DDR5 Tester Linux Options
@@ -89,18 +91,18 @@ Additionally, **etherbone** or **ethernet** can be set up with either:
 |   `--mac-address`  | MAC address to be used for the etherbone. |
 
 
-### Building DDR5 Tester Linux Target
+### Building RDIMM DDR5 Tester Linux Target
 
-After having configured the DDR5 Tester Linux, the target can be build with `make build` Makefile target.
+After having configured the RDIMM DDR5 Tester Linux, the target can be build with `make build` Makefile target.
 Use example of DDR5 Tester Linux Target with ethernet configured:
 
 ```bash
 make build TARGET=ddr5_tester_linux TARGET_ARGS="--build --l2-size 256 --iodelay-clk-freq 400e6 --module MTC10F1084S1RC --with-wishbone-memory --wishbone-force-32b --with-ethernet --remote-ip-address 192.168.100.100 --local-ip-address 192.168.100.50"
 ```
 
-### Interacting with DDR5 Tester Linux Target
+### Interacting with RDIMM DDR5 Tester Linux Target
 
-First, load the bitstream onto the DDR5 Tester with the help of the OpenFPGALoader:
+First, load the bitstream onto the RDIMM DDR5 Tester with the help of the OpenFPGALoader:
 
 ```bash
 openFPGALoader --board antmicro_ddr5_tester build/ddr5_tester_linux/gateware/antmicro_ddr5_tester.bit --freq 3e6
@@ -166,7 +168,7 @@ cd ~/ && tftp 192.168.100.100 -c get test
 
 The **test** file should appear in the home directory with "TEST TFTP SERVER" contents.
 
-### Booting Linux on DDR5 Tester Linux Target
+### Booting Linux on RDIMM DDR5 Tester Linux Target
 
 You will need the following binaries:
 - Linux kernel Image
@@ -283,4 +285,4 @@ buildroot login: root
   32-bit RISC-V Linux running on DDR5 Tester.
 
 login[65]: root login on 'console'
-```
+```

docs/source/index.md

@@ -16,9 +16,9 @@ dram_modules.md
 arty.md
 zcu104.md
 lpddr4_tb.md
+ddr5_test_board.md
 ddr4_datacenter_dram_tester.md
 ddr5_tester.md
-ddr5_test_board.md
 sodimm_ddr5_tester.md
 ```
 

docs/source/lpddr4_tb.md

@@ -13,12 +13,15 @@ The hardware is open and can be found on GitHub:
 
 ## Board configuration
 
-First insert the LPDDR4 DRAM module into the socket and make sure that jumpers are set in correct positions:
+First insert the LPDDR4 DRAM module into the socket [``](#lpddr4-test-board_) and make sure that jumpers are set in correct positions:
 
-- VDDQ (J10) should be set in position 1V1
-- MODE2 should be set in position FLASH
+- VDDQ switch ([`J7`](#lpddr4-test-board_J7)) should be set in position 1V1
+- [`MODE1`](#lpddr4-test-board_MODE1) switch should be set in position FLASH
 
-Then connect the board USB and Ethernet cables to your computer and configure the network. The board's IP address will be `192.168.100.50` (so you could e.g. use `192.168.100.2/24`). The `IP_ADDRESS` environment variable can be used to modify the board's address.
+Connect power supply (7-15VDC) to [`J6`](#lpddr4-test-board_J6) barrel jack.
+Then connect the board's USB-C [`J1`](#lpddr4-test-board_J1) and Ethernet [`J5`](#lpddr4-test-board_J5) interfaces to your computer.
+Turn the board on using power switch [`S1`](#lpddr4-test-board_S1).
+Then configure the network. The board's IP address will be `192.168.100.50` (so you could e.g. use `192.168.100.2/24`). The `IP_ADDRESS` environment variable can be used to modify the board's address.
 Next, generate the FPGA bitstream:
 
 ```sh
@@ -45,8 +48,8 @@ make flash
 ```
 
 ```{warning}
-There is a JTAG/FLASH jumper named `MODE2` on the right side of the board.
-Unless it's set to the FLASH setting, the FPGA will load the bitstream received via JTAG.
+There is a JTAG/FLASH jumper [`MODE1`](#lpddr4-test-board_MODE1) on the right side of the board.
+Unless it's set to the FLASH setting, the FPGA will load the bitstream received via JTAG ([`J4`](#lpddr4-test-board_J4)).
 ```
 
-Bitstream will be loaded from flash memory upon device power-on or after a PROG button press.
+Bitstream will be loaded from flash memory upon device power-on or after a PROG button ([`PROG_B1`](#lpddr4-test-board_PROG_B1)) press.