DSLX DMA: Github workflow #40

Job	Run time
BUILD	5m 16s
Test (test_common)	58m 35s
Test (test_csr)	1h 2m 28s
Matrix configuration	5s
Test (test_axi_csr)	1h 1m 0s
Test (test_address_generator)	1h 0m 56s
Test (test_frontend_writer)	58m 18s
Test (test_frontend_reader)	59m 26s
Test (test_main_controller)	58m 46s
Implementation (//xls/modules/dma, csr_opt_ir_benchmark, verilog_csr, csr_benchmark_synth, csr_pl...	2h 56m 56s
Implementation (//xls/modules/dma, axi_csr_opt_ir_benchmark, verilog_axi_csr, axi_csr_benchmark_s...	1h 41m 8s
Implementation (//xls/modules/dma, address_generator_opt_ir_benchmark, verilog_address_generator,...	2h 55m 12s
Implementation (//xls/modules/dma, frontend_reader_opt_ir_benchmark, verilog_frontend_reader, fro...	2h 56m 12s
Implementation (//xls/modules/dma, frontend_writer_opt_ir_benchmark, verilog_frontend_writer, fro...	2h 56m 43s
	20h 31m 1s

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