Automated Code Change

PiperOrigin-RevId: 642559590
antmicro · Jun 12, 2024 · 769ae4e · 769ae4e
1 parent 1ab57b1
commit 769ae4e
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Showing 3 changed files with 3 additions and 3 deletions.
diff --git a/xls/passes/context_sensitive_range_query_engine.cc b/xls/passes/context_sensitive_range_query_engine.cc
@@ -227,7 +227,7 @@ class Analysis {
     // arm and selector are identical
     absl::flat_hash_map<SelectorAndArm, EquivalenceSet> equivalences;
     equivalences.reserve(interesting.state_and_nodes.size());
-    for (auto [state, interesting_nodes] : interesting.state_and_nodes) {
+    for (const auto& [state, interesting_nodes] : interesting.state_and_nodes) {
       EquivalenceSet& cur =
           equivalences
               .try_emplace(

diff --git a/xls/passes/minimal_feedback_arcs.cc b/xls/passes/minimal_feedback_arcs.cc
@@ -176,7 +176,7 @@ absl::StatusOr<InterProcConnectivityGraph> MakeInterProcConnectivityGraph(
   // FunctionBase. Now, add edges between sends and receives on the same
   // channel. If there are multiple sends or receives on the same channel, add
   // an edge from every send to each receive.
-  for (auto [channel_id, send_nodes] : channel_id_to_internal_send) {
+  for (const auto& [channel_id, send_nodes] : channel_id_to_internal_send) {
     auto itr = channel_id_to_internal_receive.find(channel_id);
     if (itr == channel_id_to_internal_receive.end()) {
       XLS_ASSIGN_OR_RETURN(Channel * channel, p->GetChannel(channel_id));

diff --git a/xls/passes/proc_inlining_pass.cc b/xls/passes/proc_inlining_pass.cc
@@ -985,7 +985,7 @@ class ProcThread {
         inlined_proc_->NextState().begin(), inlined_proc_->NextState().end());
 
     std::vector<Receive*> receives;
-    for (auto [receive, nodes] : receive_data_deps) {
+    for (const auto& [receive, nodes] : receive_data_deps) {
       receives.push_back(receive);
     }
     SortByNodeId(&receives);