STM32H5 I2C Driver

Added I2C driver for the STM32H5. This driver uses the STM32H7 I2C driver as a base. The primary difference is setclock dynamically sets the I2C TIMINGR register instead of using hardcoded values. This allows the I2C peripherals to use any of the input clocks and set to any speed 0-1MHz. Additionally, Kconfig options were made available to set the Digital Noise Filter (DNF), Analog Noise Filter, I2C Clock source (i2c_ker_ck), as well as set i2c rise/fall times which are crucial to timing. Care must be taken when setting the clock source and filters, as not all settings are compatible with all i2c clock frequencies.

arch/arm/src/stm32h5/Kconfig

@@ -366,6 +366,30 @@ config STM32H5_LPUART1
 	select ARCH_HAVE_SERIAL_TERMIOS
 	select STM32H5_USART
 
+config STM32H5_I2C
+        bool
+        default n
+
+config STM32H5_I2C1
+	bool "I2C1"
+	default n
+	select STM32H5_I2C
+
+config STM32H5_I2C2
+	bool "I2C2"
+	default n
+	select STM32H5_I2C
+
+config STM32H5_I2C3
+	bool "I2C3"
+	default n
+	select STM32H5_I2C
+
+config STM32H5_I2C4
+	bool "I2C4"
+	default n
+	select STM32H5_I2C
+
 endmenu
 
 
@@ -1061,4 +1085,212 @@ config STM32H5_NO_PHY
 
 endmenu # Ethernet MAC Configuration
 
+
+menu "I2C Configuration"
+	depends on STM32H5_I2C
+
+menu "Clock Selection"
+
+choice
+        depends on STM32H5_I2C1
+        prompt "I2C1 Input Clock Selection"
+        default STM32H5_I2C1_CLK_PCLK1
+config STM32H5_I2C1_CLK_CSI
+        bool "CSI"
+config STM32H5_I2C1_CLK_HSI
+        bool "HSI"
+config STM32H5_I2C1_CLK_PCLK1
+        bool "PCLK1"
+config STM32H5_I2C1_CLK_PLL3R
+        bool "PLL3R"
+endchoice
+choice
+        depends on STM32H5_I2C2
+        prompt "I2C2 Input Clock Selection"
+        default STM32H5_I2C2_CLK_PCLK1
+config STM32H5_I2C2_CLK_CSI
+        bool "CSI"
+config STM32H5_I2C2_CLK_HSI
+        bool "HSI"
+config STM32H5_I2C2_CLK_PCLK1
+        bool "PCLK1"
+config STM32H5_I2C2_CLK_PLL3R
+        bool "PLL3R"
+endchoice
+choice
+        depends on STM32H5_I2C3
+        prompt "I2C3 Input Clock Selection"
+        default STM32H5_I2C3_CLK_PCLK3
+config STM32H5_I2C3_CLK_CSI
+        bool "CSI"
+config STM32H5_I2C3_CLK_HSI
+        bool "HSI"
+config STM32H5_I2C3_CLK_PCLK3
+        bool "PCLK3"
+config STM32H5_I2C3_CLK_PLL3R
+        bool "PLL3R"
+endchoice
+choice
+        depends on STM32H5_I2C4
+        prompt "I2C4 Input Clock Selection"
+        default STM32H5_I2C4_CLK_PCLK3
+config STM32H5_I2C4_CLK_CSI
+        bool "CSI"
+config STM32H5_I2C4_CLK_HSI
+        bool "HSI"
+config STM32H5_I2C4_CLK_PCLK3
+        bool "PCLK3"
+config STM32H5_I2C4_CLK_PLL3R
+        bool "PLL3R"
+endchoice
+
+endmenu
+
+menu "Rise/Fall Override"
+config STM32H5_I2C1_RF_OVERRIDE
+        bool "I2C1"
+        default n
+        depends on STM32H5_I2C1
+config STM32H5_I2C2_RF_OVERRIDE
+        bool "I2C2"
+        default n
+        depends on STM32H5_I2C2
+config STM32H5_I2C3_RF_OVERRIDE
+        bool "I2C3"
+        default n
+        depends on STM32H5_I2C3
+config STM32H5_I2C4_RF_OVERRIDE
+        bool "I2C4"
+        default n
+        depends on STM32H5_I2C4
+
+menu "Rise/Fall Values"
+config STM32H5_I2C1_RISE
+        int "I2C1 Rise Time (ns)"
+        range 0 1000
+        default 20
+        depends on STM32H5_I2C1_RF_OVERRIDE
+config STM32H5_I2C1_FALL
+        int "I2C1 Fall Time (ns)"
+        range 0 300
+        default 20
+        depends on STM32H5_I2C1_RF_OVERRIDE
+config STM32H5_I2C2_RISE
+        int "I2C2 Rise Time (ns)"
+        range 0 1000
+        default 20
+        depends on STM32H5_I2C2_RF_OVERRIDE
+config STM32H5_I2C2_FALL
+        int "I2C2 Fall Time (ns)"
+        range 0 300
+        default 20
+        depends on STM32H5_I2C2_RF_OVERRIDE
+config STM32H5_I2C3_RISE
+        int "I2C3 Rise Time (ns)"
+        range 0 1000
+        default 20
+        depends on STM32H5_I2C3_RF_OVERRIDE
+config STM32H5_I2C3_FALL
+        int "I2C3 Fall Time (ns)"
+        range 0 300
+        default 20
+        depends on STM32H5_I2C3_RF_OVERRIDE
+config STM32H5_I2C4_RISE
+        int "I2C4 Rise Time (ns)"
+        range 0 1000
+        default 20
+        depends on STM32H5_I2C4_RF_OVERRIDE
+config STM32H5_I2C4_FALL
+        int "I2C4 Fall Time (ns)"
+        range 0 300
+        default 20
+        depends on STM32H5_I2C4_RF_OVERRIDE
+endmenu
+endmenu
+
+menu "Filtering"
+
+menu "Digital Filters"
+config STM32H5_I2C1_DNF
+        int "I2C1 Digital Noise Filter"
+        range 0 15
+        default 0
+        depends on STM32H5_I2C1
+config STM32H5_I2C2_DNF
+        int "I2C2 Digital Noise Filter"
+        range 0 15
+        default 0
+        depends on STM32H5_I2C2
+config STM32H5_I2C3_DNF
+        int "I2C3 Digital Noise Filter"
+        range 0 15
+        default 0
+        depends on STM32H5_I2C3
+config STM32H5_I2C4_DNF
+        int "I2C4 Digital Noise Filter"
+        range 0 15
+        default 0
+        depends on STM32H5_I2C4
+endmenu
+
+menu "Analog Filters"
+config STM32H5_I2C1_ANFOFF
+        int "Turn off I2C1 Analog Filter (0=on, 1=off)"
+        default 1
+        range 0 1
+        depends on STM32H5_I2C1
+
+config STM32H5_I2C2_ANFOFF
+        int "Turn off I2C2 Analog Filter (0=on, 1=off)"
+        default 1
+        range 0 1
+        depends on STM32H5_I2C2
+
+config STM32H5_I2C3_ANFOFF
+        int "Turn off I2C3 Analog Filter (0=on, 1=off)"
+        default 1
+        range 0 1
+        depends on STM32H5_I2C3
+
+config STM32H5_I2C4_ANFOFF
+        int "Turn off I2C4 Analog Filter (0=on, 1=off)"
+        default 1
+        range 0 1
+        depends on STM32H5_I2C4
+endmenu
+
+endmenu
+
+config STM32H5_I2C_DYNTIMEO
+	bool "Use dynamic timeouts"
+	default n
+	depends on STM32H5_I2C
+
+config STM32H5_I2C_DYNTIMEO_USECPERBYTE
+	int "Timeout Microseconds per Byte"
+	default 500
+	depends on STM32H5_I2C_DYNTIMEO
+
+config STM32H5_I2C_DYNTIMEO_STARTSTOP
+	int "Timeout for Start/Stop (Milliseconds)"
+	default 1000
+	depends on STM32H5_I2C_DYNTIMEO
+
+config STM32H5_I2CTIMEOSEC
+	int "Timeout seconds"
+	default 0
+	depends on STM32H5_I2C
+
+config STM32H5_I2CTIMEOMS
+	int "Timeout Milliseconds"
+	default 500
+	depends on STM32H5_I2C && !STM32H5_I2C_DYNTIMEO
+
+config STM32H5_I2CTIMEOTICKS
+	int "Timeout for Done and Stop (ticks)"
+	default 500
+	depends on STM32H5_I2C && !STM32H5_I2C_DYNTIMEO
+
+endmenu # "I2C Configuration"
+
 endif # ARCH_CHIP_STM32H5

arch/arm/src/stm32h5/Make.defs

@@ -44,6 +44,10 @@ ifeq ($(CONFIG_TIMER),y)
 CHIP_CSRCS += stm32h5_tim_lowerhalf.c
 endif
 
+ifeq ($(CONFIG_STM32H5_I2C),y)
+CHIP_CSRCS += stm32_i2c.c
+endif
+
 # Required chip type specific files
 
 ifeq ($(CONFIG_STM32H5_STM32H5XXXX),y)

arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h

@@ -100,6 +100,42 @@
 
 #define GPIO_MCO_0             (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN8)
 
+/* I2C */
+
+#define GPIO_I2C1_SDA_1        (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_I2C1_SDA_2        (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_I2C1_SCL_1        (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_I2C1_SCL_2        (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_I2C1_SMBA_1       (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN5)
+
+#define GPIO_I2C2_SDA_1        (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_I2C2_SDA_2        (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_I2C2_SDA_3        (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_I2C2_SDA_4        (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN5)
+#define GPIO_I2C2_SCL_1        (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_I2C2_SCL_2        (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN1)
+#define GPIO_I2C2_SCL_3        (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN4)
+#define GPIO_I2C2_SMBA_1       (GPIO_ALT|GPIO_AF4|GPIO_PORTH|GPIO_PIN6)
+
+#define GPIO_I2C3_SDA_1        (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN9)
+#define GPIO_I2C3_SDA_2        (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN8)
+#define GPIO_I2C3_SCL_1        (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_I2C3_SCL_2        (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN7)
+#define GPIO_I2C3_SMBA_1       (GPIO_ALT|GPIO_AF4|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_I2C3_SMBA_2       (GPIO_ALT|GPIO_AF4|GPIO_PORTH|GPIO_PIN9)
+
+#define GPIO_I2C4_SDA_1        (GPIO_ALT|GPIO_AF6|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_I2C4_SDA_2        (GPIO_ALT|GPIO_AF6|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_I2C4_SDA_3        (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN13)
+#define GPIO_I2C4_SDA_4        (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN15)
+#define GPIO_I2C4_SCL_1        (GPIO_ALT|GPIO_AF6|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_I2C4_SCL_2        (GPIO_ALT|GPIO_AF6|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_I2C4_SCL_3        (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN12)
+#define GPIO_I2C4_SCL_4        (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN5)
+#define GPIO_I2C4_SMBA_1       (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_I2C4_SMBA_2       (GPIO_ALT|GPIO_AF4|GPIO_PORTD|GPIO_PIN11)
+#define GPIO_I2C4_SMBA_3       (GPIO_ALT|GPIO_AF4|GPIO_PORTF|GPIO_PIN13)
+
 /* JTAG */
 
 #define GPIO_JTCK_SWCLK_0      (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14)