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arm64: fix tpidr maybe null #15338
arm64: fix tpidr maybe null #15338
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[Experimental Bot, please feedback here] Yes, this PR likely meets the basic NuttX requirements but is missing crucial information. Here's why it's borderline and what's missing:
To make this PR acceptable, you need to add the missing details outlined above. Specifically, clarify how the fix works, expand on the impact section answering all the questions, and provide detailed build host information and actual before/after logs demonstrating the fix. |
Before the MPU initialization, the up_update_task(this_cpu()) function is called at a time when hardware cache coherency is not yet enabled. In certain critical scenarios, Core 1 reads a zero value for tcb from the global variable g_assignedtask and stores this zero value into the tpidr register. This results in subsequent interrupt handlers reading a zero tcb, causing an exception. Signed-off-by: hujun5 <[email protected]>
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/* Init idle task to percpu reg */ | ||
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up_update_task(current_task(this_cpu())); |
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do we need change other arch too
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Yes, the current community code implements percpu storage for this_task on arm64, armv7a, armv7r, and armv8r archs, all using this approach.
Note: Please adhere to Contributing Guidelines.
Summary
arm64: fix tpidr maybe null
Before the MPU initialization, the up_update_task(this_cpu()) function is called at a time when hardware cache coherency is not yet enabled. In certain critical scenarios, Core 1 reads a zero value for tcb from the global variable g_assignedtask and stores this zero value into the tpidr register. This results in subsequent interrupt handlers reading a zero tcb, causing an exception.
Impact
arm64
Testing
qemu-armv8a:nsh_smp