Generate .inst via Python

.gitignore

@@ -3,6 +3,7 @@
 # generated Python and Verilog Verilog
 *.v
 *.py
+*.inst
 
 # macOS
 .DS_Store

.vscode/extensions.json

@@ -1,5 +1,6 @@
 {
     "recommendations": [
-        "rust-lang.rust-analyzer"
+        "rust-lang.rust-analyzer",
+        "redhat.vscode-yaml"
     ]
 }

.vscode/settings.json

@@ -1,5 +1,8 @@
 {
     "rust-analyzer.cargo.features": "all",
+    "files.associations": {
+        "*.inst": "yaml"
+    },
     "cSpell.words": [
         "pytv"
     ]

examples/test.pytv

@@ -9,6 +9,6 @@ Do nothing here either! { some content }
 //! module: test
 //! name: inst_test
 //! parameters:
-//!  - name1: value1
-//!  - name2: value2
+//!   - name1: value1
+//!   - name2: value2
 //! </INST>

src/convert.rs

@@ -38,6 +38,7 @@ impl Convert {
     }
 
     /// Opens the output Python file and returns a file handle.
+    ///
     /// Note: This will overwrite the existing file.
     fn open_output(&self) -> IoResult<std::fs::File> {
         std::fs::File::create(&self.output_python_file_name())
@@ -66,6 +67,11 @@ impl Convert {
         self.output_file_name() + ".py"
     }
 
+    /// Generates the output instantiation file name based on the input file name and configuration.
+    fn output_inst_file_name(&self) -> String {
+        self.output_file_name() + ".inst"
+    }
+
     /// Checks if a line of code is a Python line based on the magic comment string in the configuration.
     fn if_py_line(&self, line: &str) -> bool {
         line.trim_start()
@@ -149,6 +155,8 @@ impl Convert {
         #[cfg(feature = "inst")]
         let mut within_inst = false;
         let mut inst_str = String::new();
+        #[cfg(feature = "inst")]
+        writeln!(stream, "_inst_file = open('{}', 'w')", self.output_inst_file_name())?;
         // parse line by line
         for line in self.open_input()?.lines() {
             let line = self.pre_process_line(&line);
@@ -159,14 +167,22 @@ impl Convert {
                     py_indent_space = line.chars().position(|c| !c.is_whitespace()).unwrap_or(0);
                 }
                 #[cfg(feature = "inst")]
-                self.process_python_line(&line, py_indent_space, &mut stream, &mut within_inst, &mut inst_str)?;
+                self.process_python_line(
+                    &line,
+                    py_indent_space,
+                    &mut stream,
+                    &mut within_inst,
+                    &mut inst_str,
+                )?;
                 #[cfg(not(feature = "inst"))]
                 self.process_python_line(&line, py_indent_space, &mut stream)?;
             } else {
                 let line = self.apply_verilog_regex(self.escape_verilog(&line).as_str());
                 writeln!(stream, "print(f'{line}')")?;
             }
         }
+        #[cfg(feature = "inst")]
+        writeln!(stream, "_inst_file.close()")?;
         Ok(())
     }
 

src/inst.rs

@@ -56,8 +56,8 @@ impl Convert {
     }
 
     fn print_inst<W: Write>(&self, stream: &mut W, inst_str: &str) -> Result<(), Box<dyn Error>> {
-        // TODO: process YML and write to file
-        writeln!(stream, "{}", inst_str)?;
+        // TODO: process YML
+        writeln!(stream, "_inst_file.write('''{}''')", inst_str)?;
         Ok(())
     }
 }