fix(riscv): add low order bits to faulting address

Signed-off-by: Jose Martins <[email protected]>
bao-project · Nov 4, 2024 · 9bfb820 · 9bfb820
1 parent 6df80f4
commit 9bfb820
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/arch/riscv/sync_exceptions.c b/src/arch/riscv/sync_exceptions.c
@@ -80,7 +80,7 @@ static inline bool is_pseudo_ins(uint32_t ins)
 
 static size_t guest_page_fault_handler(void)
 {
-    vaddr_t addr = csrs_htval_read() << 2;
+    vaddr_t addr = (csrs_htval_read() << 2) | (csrs_stval_read() & 0x3);
 
     emul_handler_t handler = vm_emul_get_mem(cpu()->vcpu->vm, addr);
     if (handler != NULL) {