Merge pull request #94 from turol/fix_typos

Fix typos in comments
bitdefender · Jul 29, 2024 · 2b1c90b · 2b1c90b
2 parents 1fa2ee4 + c008c46
commit 2b1c90b
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/bddisasm/bdx86_decoder.c b/bddisasm/bdx86_decoder.c
@@ -1894,7 +1894,7 @@ NdParseOperand(
         // Fill in branch information.
         Instrux->BranchInfo.IsBranch = 1;
         Instrux->BranchInfo.IsConditional = Instrux->Category == ND_CAT_COND_BR;
-        // Indirect branches are those which get their target address from a register or memory, including RET familly.
+        // Indirect branches are those which get their target address from a register or memory, including RET family.
         Instrux->BranchInfo.IsIndirect = ((!Instrux->Operands[0].Flags.IsDefault) && 
             ((Instrux->Operands[0].Type == ND_OP_REG) || (Instrux->Operands[0].Type == ND_OP_MEM))) || 
             (Instrux->Category == ND_CAT_RET);

diff --git a/bddisasm/include/bdx86_tabledefs.h b/bddisasm/include/bdx86_tabledefs.h
@@ -279,7 +279,7 @@ typedef struct _ND_IDBE
 
 
 //
-// Operand sizes descriptors. These are internal and stored inside the specifier. They must be interpreted
+// Operand size descriptors. These are internal and stored inside the specifier. They must be interpreted
 // accordingly to extract the actual size used in the instruction. These should not be used by anyone using
 // the disassembler. Use the "Size" and "RawSize" fields inside the operand instead.
 //
@@ -418,7 +418,7 @@ typedef enum _ND_OPERAND_TYPE_SPEC
     ND_OPT_SSP,
     ND_OPT_UIF,
 
-    // General Purpose REgisters.
+    // General Purpose Registers.
     ND_OPT_AH,
     ND_OPT_rAX,
     ND_OPT_rCX,