Added support for new Intel ISA, per Intel® Architecture Instruction …

…Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
bitdefender · Jul 21, 2023 · f53cbc5 · f53cbc5
1 parent be09698
commit f53cbc5
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diff --git a/bddisasm/include/instructions.h b/bddisasm/include/instructions.h
diff --git a/bddisasm/include/mnemonics.h b/bddisasm/include/mnemonics.h
diff --git a/bddisasm/include/table_evex.h b/bddisasm/include/table_evex.h
diff --git a/bddisasm/include/table_root.h b/bddisasm/include/table_root.h
diff --git a/bddisasm/include/table_vex.h b/bddisasm/include/table_vex.h
diff --git a/bddisasm/include/table_xop.h b/bddisasm/include/table_xop.h
diff --git a/bddisasm_test/x86/avx/avxvnniint16_64.asm b/bddisasm_test/x86/avx/avxvnniint16_64.asm
@@ -0,0 +1,35 @@
+        bits 64
+        
+        db 0xc4, 0x62, 0x78, 0xd2, 0xc7         ; VPDPWUUD  xmm8, xmm0, xmm7
+        db 0xc4, 0x62, 0x78, 0xd2, 0x01         ; VPDPWUUD  xmm8, xmm0, xmmword ptr [rcx]
+        db 0xc4, 0x62, 0x78, 0xd3, 0xc7         ; VPDPWUUDS xmm8, xmm0, xmm7
+        db 0xc4, 0x62, 0x78, 0xd3, 0x01         ; VPDPWUUDS xmm8, xmm0, xmmword ptr [rcx]
+        
+        db 0xc4, 0x62, 0x79, 0xd2, 0xc7         ; VPDPWUSD  xmm8, xmm0, xmm7
+        db 0xc4, 0x62, 0x79, 0xd2, 0x01         ; VPDPWUSD  xmm8, xmm0, xmmword ptr [rcx]
+        db 0xc4, 0x62, 0x79, 0xd3, 0xc7         ; VPDPWUSDS xmm8, xmm0, xmm7
+        db 0xc4, 0x62, 0x79, 0xd3, 0x01         ; VPDPWUSDS xmm8, xmm0, xmmword ptr [rcx]
+        
+        db 0xc4, 0x62, 0x7a, 0xd2, 0xc7         ; VPDPWSUD  xmm8, xmm0, xmm7
+        db 0xc4, 0x62, 0x7a, 0xd2, 0x01         ; VPDPWSUD  xmm8, xmm0, xmmword ptr [rcx]
+        db 0xc4, 0x62, 0x7a, 0xd3, 0xc7         ; VPDPWSUDS xmm8, xmm0, xmm7
+        db 0xc4, 0x62, 0x7a, 0xd3, 0x01         ; VPDPWSUDS xmm8, xmm0, xmmword ptr [rcx]
+        
+        
+        db 0xc4, 0x62, 0x7c, 0xd2, 0xc7         ; VPDPWUUD  ymm8, ymm0, ymm7
+        db 0xc4, 0x62, 0x7c, 0xd2, 0x01         ; VPDPWUUD  ymm8, ymm0, ymmword ptr [rcx]
+        db 0xc4, 0x62, 0x7c, 0xd3, 0xc7         ; VPDPWUUDS ymm8, ymm0, ymm7
+        db 0xc4, 0x62, 0x7c, 0xd3, 0x01         ; VPDPWUUDS ymm8, ymm0, ymmword ptr [rcx]
+        
+        db 0xc4, 0x62, 0x7d, 0xd2, 0xc7         ; VPDPWUSD  ymm8, ymm0, ymm7
+        db 0xc4, 0x62, 0x7d, 0xd2, 0x01         ; VPDPWUSD  ymm8, ymm0, ymmword ptr [rcx]
+        db 0xc4, 0x62, 0x7d, 0xd3, 0xc7         ; VPDPWUSDS ymm8, ymm0, ymm7
+        db 0xc4, 0x62, 0x7d, 0xd3, 0x01         ; VPDPWUSDS ymm8, ymm0, ymmword ptr [rcx]
+        
+        db 0xc4, 0x62, 0x7e, 0xd2, 0xc7         ; VPDPWSUD  ymm8, ymm0, ymm7
+        db 0xc4, 0x62, 0x7e, 0xd2, 0x01         ; VPDPWSUD  ymm8, ymm0, ymmword ptr [rcx]
+        db 0xc4, 0x62, 0x7e, 0xd3, 0xc7         ; VPDPWSUDS ymm8, ymm0, ymm7
+        db 0xc4, 0x62, 0x7e, 0xd3, 0x01         ; VPDPWSUDS ymm8, ymm0, ymmword ptr [rcx]
+        
+        
+    
diff --git a/bddisasm_test/x86/avx/avxvnniint16_64.result b/bddisasm_test/x86/avx/avxvnniint16_64.result
diff --git a/bddisasm_test/x86/avx/avxvnniint16_64.test b/bddisasm_test/x86/avx/avxvnniint16_64.test
@@ -0,0 +1 @@
+�bx���bx��bx���bx��by���by��by���by��bz���bz��bz���bz��b|���b|��b|���b|��b}���b}��b}���b}��b~���b~��b~���b~�
diff --git a/bddisasm_test/x86/sha512/sha512_64.asm b/bddisasm_test/x86/sha512/sha512_64.asm
@@ -0,0 +1,7 @@
+        bits 64
+        
+        db 0xc4, 0x62, 0x7f, 0xcb, 0xc7         ; VSHA512RNDS2 ymm8, ymm0, xmm7
+        db 0xc4, 0x62, 0x7f, 0xcc, 0xc7         ; VSHA512MSG1 ymm8, xmm7
+        db 0xc4, 0x62, 0x7f, 0xcd, 0xc7         ; VSHA512MSG2 ymm8, ymm7
+        db 0xc4, 0x63, 0x79, 0xde, 0xc7, 0xef   ; VSM3RNDS2 xmm8, xmm0, xmm7, 0xef
+        db 0xc4, 0x63, 0x79, 0xde, 0x01, 0xef   ; VSM3RNDS2 xmm8, xmm0, xmmword ptr [rcx], 0xef
diff --git a/bddisasm_test/x86/sha512/sha512_64.result b/bddisasm_test/x86/sha512/sha512_64.result
@@ -0,0 +1,91 @@
+0000000000000000 c4627fcbc7                      VSHA512RNDS2 ymm8, ymm0, xmm7
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: SHA512, Ins cat: SHA512, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 0
+        Exception class: SSE/VEX, exception type: 6
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: V, RegType:           Vector, RegSize: 32, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 7, RegCount: 1
+
+0000000000000005 c4627fccc7                      VSHA512MSG1 ymm8, xmm7
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: SHA512, Ins cat: SHA512, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 0
+        Exception class: SSE/VEX, exception type: 6
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 7, RegCount: 1
+
+000000000000000A c4627fcdc7                      VSHA512MSG2 ymm8, ymm7
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: SHA512, Ins cat: SHA512, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 0
+        Exception class: SSE/VEX, exception type: 6
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: M, RegType:           Vector, RegSize: 32, RegId: 7, RegCount: 1
+
+000000000000000F c46379dec7ef                    VSM3RNDS2 xmm8, xmm0, xmm7, 0xef
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: SM3, Ins cat: SM3, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 1
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 7, RegCount: 1
+        Operand: 3, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: I
+
+0000000000000015 c46379de01ef                    VSM3RNDS2 xmm8, xmm0, xmmword ptr [rcx], 0xef
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: SM3, Ins cat: SM3, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 1
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 16, RawSize: 16, Encoding: M, 
+                Segment: 3, Base: 1, 
+        Operand: 3, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: I
+
diff --git a/bddisasm_test/x86/sha512/sha512_64.test b/bddisasm_test/x86/sha512/sha512_64.test
@@ -0,0 +1 @@
+�b���b���b���cy����cy��
diff --git a/bddisasm_test/x86/sm/sm_64.asm b/bddisasm_test/x86/sm/sm_64.asm
@@ -0,0 +1,19 @@
+        bits 64
+        
+        db 0xc4, 0x62, 0x78, 0xda, 0xc7         ; VSM3MSG1  xmm8, xmm0, xmm7
+        db 0xc4, 0x62, 0x78, 0xda, 0x01         ; VSM3MSG1  xmm8, xmm0, xmmword ptr [rcx]
+        db 0xc4, 0x62, 0x79, 0xda, 0xc7         ; VSM3MSG2  xmm8, xmm0, xmm7
+        db 0xc4, 0x62, 0x79, 0xda, 0x01         ; VSM3MSG2  xmm8, xmm0, xmmword ptr [rcx]
+        
+        db 0xc4, 0x62, 0x7a, 0xda, 0xc7         ; VSM4KEY4  xmm8, xmm0, xmm7
+        db 0xc4, 0x62, 0x7a, 0xda, 0x01         ; VSM4KEY4  xmm8, xmm0, xmmword ptr [rcx]
+        db 0xc4, 0x62, 0x7b, 0xda, 0xc7         ; VSM4RNDS4 xmm8, xmm0, xmm7
+        db 0xc4, 0x62, 0x7b, 0xda, 0x01         ; VSM4RNDS4 xmm8, xmm0, xmmword ptr [rcx]
+        
+        db 0xc4, 0x62, 0x7e, 0xda, 0xc7         ; VSM4KEY4  ymm8, ymm0, ymm7
+        db 0xc4, 0x62, 0x7e, 0xda, 0x01         ; VSM4KEY4  ymm8, ymm0, ymmword ptr [rcx]
+        db 0xc4, 0x62, 0x7f, 0xda, 0xc7         ; VSM4RNDS4 ymm8, ymm0, ymm7
+        db 0xc4, 0x62, 0x7f, 0xda, 0x01         ; VSM4RNDS4 ymm8, ymm0, ymmword ptr [rcx]
+        
+        db 0xc4, 0x63, 0x79, 0xde, 0xc7, 0xef   ; VSM3RNDS2 xmm8, xmm0, xmm7, 0xef
+        db 0xc4, 0x63, 0x79, 0xde, 0x01, 0xef   ; VSM3RNDS2 xmm8, xmm0, xmmword ptr [rcx], 0xef