Banjo Tooie checksum routine

Update: A complete comparison of the disassembly in all 4 games is here: https://github.com/bryc/rare-n64-chksm/wiki/Checksum-code-disassembly. So this old page has repetitive info.

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First Loop (Banjo Tooie)

Load byte unsigned

    801928A4:    LBU        T8, 0x0000 (S0)
    801928A8:    LW         T5, 0x004C (SP)
    801928AC:    ANDI       T9, S1, 0x000F
    801928B0:    SLLV       T0, T8, T9
    801928B4:    LW         T4, 0x0048 (SP)
    801928B8:    ADDU       T7, T0, T5
    801928BC:    SRA        T2, T0, 0x1F
    801928C0:    SLTU       AT, T7, T5
    801928C4:    ADDU       T6, AT, T2
    801928C8:    ADDU       T6, T6, T4
    801928CC:    SW         T6, 0x0048 (SP)
    801928D0:    SW         T7, 0x004C (SP)
    801928D4:    JAL        0x801168AC       
    801928D8:    OR         A0, S2, R0

The Algorithm (Bit shifting, XOR etc)

    801168AC:    LD         A3, 0x0000 (A0)
    801168B0:    DSLL32     A2, A3, 0x1F
    801168B4:    DSLL       A1, A3, 0x1F
    801168B8:    DSRL       A2, A2, 0x1F
    801168BC:    DSRL32     A1, A1, 0x0
    801168C0:    DSLL32     A3, A3, 0xC
    801168C4:    OR         A2, A2, A1
    801168C8:    DSRL32     A3, A3, 0x0
    801168CC:    XOR        A2, A2, A3
    801168D0:    DSRL       A3, A2, 0x14
    801168D4:    ANDI       A3, A3, 0x0FFF
    801168D8:    XOR        A3, A3, A2
    801168DC:    DSLL32     V0, A3, 0x0
    801168E0:    SD         A3, 0x0000 (A0)
    801168E4:    JR         RA                   ; RA = 801928DC
    801168E8:    DSRA32     V0, V0, 0x0

Jumps back to increase counters, then continue loop

    801928DC:    ADDIU      S0, S0, 0x0001
    801928E0:    ADDIU      S1, S1, 0x0007
    801928E4:    BNE        S0, S5, 0x801928A4
    801928E8:    XOR        S3, S3, V0

Second Loop

Load byte unsigned

    80192904:    LBU        T1, 0x0000 (S0)
    80192908:    LW         T3, 0x004C (SP)
    8019290C:    ANDI       T8, S1, 0x000F
    80192910:    SLLV       T9, T1, T8
    80192914:    LW         T2, 0x0048 (SP)
    80192918:    ADDU       T5, T9, T3
    8019291C:    SRA        T0, T9, 0x1F
    80192920:    SLTU       AT, T5, T3
    80192924:    ADDU       T4, AT, T0
    80192928:    ADDU       T4, T4, T2
    8019292C:    SW         T4, 0x0048 (SP)
    80192930:    SW         T5, 0x004C (SP)
    80192934:    JAL        0x801168AC
    80192938:    OR         A0, S2, R0

Same algorithm as before

    801168AC:    LD         A3, 0x0000 (A0)
    801168B0:    DSLL32     A2, A3, 0x1F
    801168B4:    DSLL       A1, A3, 0x1F
    801168B8:    DSRL       A2, A2, 0x1F
    801168BC:    DSRL32     A1, A1, 0x0
    801168C0:    DSLL32     A3, A3, 0xC
    801168C4:    OR         A2, A2, A1
    801168C8:    DSRL32     A3, A3, 0x0
    801168CC:    XOR        A2, A2, A3
    801168D0:    DSRL       A3, A2, 0x14
    801168D4:    ANDI       A3, A3, 0x0FFF
    801168D8:    XOR        A3, A3, A2
    801168DC:    DSLL32     V0, A3, 0x0
    801168E0:    SD         A3, 0x0000 (A0)
    801168E4:    JR         RA                   ; RA = 8019293C
    801168E8:    DSRA32     V0, V0, 0x0

In the second loop, one counter decreases by 1, the other increases by 3

    8019293C:    ADDIU      S0, S0, 0xFFFF
    80192940:    ADDIU      S1, S1, 0x0003
    80192944:    BNE        S0, S5, 0x80192904
    80192948:    XOR        S4, S4, V0