Refactor ARC

arch/ARC/ARCMapping.c

@@ -157,7 +157,6 @@ void ARC_printer(MCInst *MI, SStream *O,
 	MI->MRI = MRI;
 
 	ARC_LLVM_printInst(MI, MI->address, "", O);
-	// ARC_add_cs_groups(MI);
 }
 
 void ARC_setup_op(cs_arc_op *op)
@@ -168,17 +167,18 @@ void ARC_setup_op(cs_arc_op *op)
 
 void ARC_init_cs_detail(MCInst *MI)
 {
-	if (detail_is_set(MI)) {
-		unsigned int i;
+	if (!detail_is_set(MI)) {
+		return;
+	}
+	unsigned int i;
 
-		memset(get_detail(MI), 0,
-		       offsetof(cs_detail, arc) + sizeof(cs_arc));
+	memset(get_detail(MI), 0,
+			offsetof(cs_detail, arc) + sizeof(cs_arc));
 
-		for (i = 0; i < ARR_SIZE(ARC_get_detail(MI)->operands);
-		     i++)
-			ARC_setup_op(
-				&ARC_get_detail(MI)->operands[i]);
-	}
+	for (i = 0; i < ARR_SIZE(ARC_get_detail(MI)->operands);
+			i++)
+		ARC_setup_op(
+			&ARC_get_detail(MI)->operands[i]);
 }
 
 static const map_insn_ops insn_operands[] = {
@@ -191,8 +191,8 @@ void ARC_set_detail_op_imm(MCInst *MI, unsigned OpNum,
 	if (!detail_is_set(MI))
 		return;
 	ARC_check_safe_inc(MI);
-	assert((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_IMM);
-	assert(ImmType == ARC_OP_IMM);
+	CS_ASSERT((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_IMM);
+	CS_ASSERT(ImmType == ARC_OP_IMM);
 
 	ARC_get_detail_op(MI, 0)->type = ImmType;
 	ARC_get_detail_op(MI, 0)->imm = Imm;
@@ -205,7 +205,7 @@ void ARC_set_detail_op_reg(MCInst *MI, unsigned OpNum, arc_reg Reg)
 	if (!detail_is_set(MI))
 		return;
 	ARC_check_safe_inc(MI);
-	assert((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG);
+	CS_ASSERT((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG);
 
 	ARC_get_detail_op(MI, 0)->type = ARC_OP_REG;
 	ARC_get_detail_op(MI, 0)->reg = Reg;

arch/ARC/ARCMapping.h

@@ -4,6 +4,7 @@
 #ifndef CS_ARC_MAP_H
 #define CS_ARC_MAP_H
 
+#include "../../Mapping.h"
 #include "../../include/capstone/capstone.h"
 #include "../../utils.h"
 
@@ -43,7 +44,7 @@ void ARC_add_cs_detail(MCInst *MI, int /* arc_op_group */ op_group,
 static inline void add_cs_detail(MCInst *MI,
 				 int /* arc_op_group */ op_group, ...)
 {
-	if (!MI->flat_insn->detail)
+	if (!detail_is_set(MI))
 		return;
 	va_list args;
 	va_start(args, op_group);

bindings/python/capstone/arc.py

@@ -14,9 +14,9 @@ class ARCOpValue(ctypes.Union):
 
 class ARCOp(ctypes.Structure):
     _fields_ = (
-        ('type', ctypes.c_uint),
+        ('type', ctypes.c_int),
         ('value', ARCOpValue),
-        ('access', ctypes.c_uint8)
+        ('access', ctypes.c_uint)
     )
 
     @property
@@ -33,7 +33,6 @@ class CsARC(ctypes.Structure):
     _fields_ = (
         ('op_count', ctypes.c_uint8),
         ('operands', ARCOp * 8),
-        ('update_flags', ctypes.c_bool),
     )
 
 def get_arch_info(a):

cstool/cstool.c

@@ -363,11 +363,6 @@ static void usage(char *prog)
 		printf(")\n");
 	}
 
-	if (cs_support(CS_ARCH_ARC)) {
-		printf("        arc         arc little endian\n");
-		printf("        arcbe       arc big endian\n");
-	}
-
 	printf("\nExtra options:\n");
 	printf("        -d show detailed information of the instructions\n");
 	printf("        -r show detailed information of the real instructions (even for alias)\n");

include/capstone/arc.h

@@ -19,21 +19,12 @@ typedef enum arc_op_type {
 	ARC_OP_IMM = CS_OP_IMM,	      ///< Immediate operand
 } arc_op_type;
 
-// /// Instruction's operand referring to memory
-// /// This is associated with ARC_OP_MEM operand type above
-// typedef struct arc_op_mem {
-// 	unsigned int base;  ///< base register
-// 	unsigned int index; ///< index register
-// 	int64_t disp;	    ///< displacement/offset value
-// } arc_op_mem;
-
 /// Instruction operand
 typedef struct cs_arc_op {
 	arc_op_type type;	      //< operand type
 	union {
 		unsigned int reg;     /// register value for REG operand
 		int64_t imm;	      /// immediate value for IMM operand
-		// arc_op_mem mem; /// base/disp value for MEM operand
 	};
 
 	/// How is this operand accessed? (READ, WRITE or READ|WRITE)

suite/auto-sync/src/autosync/Targets.py

@@ -38,7 +38,6 @@
     "LoongArch": "LoongArch",
     "SystemZ": "SystemZ",
     "Mips": "Mips",
-    "ARC": "ARC",
     "Xtensa": "Xtensa",
     "TriCore": "TriCore",
     "ARC": "ARC",

suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py

@@ -433,15 +433,10 @@ def translate(self) -> None:
                 # Each patch has a capture which includes the whole subtree searched for.
                 # Additionally, it can include captures within this subtree.
                 # Here we bundle these captures together.
-                # if "template_declaration" in pattern:
-                #     print(self.tree.root_node)
                 query: Query = self.ts_cpp_lang.query(pattern)
                 captures_bundle: [[(Node, str)]] = list()
                 for q in query.captures(self.tree.root_node):
                     if q[1] == patch.get_main_capture_name():
-                        # from autosync.cpptranslator.patches.Helper import get_text
-                        # if patch.get_main_capture_name() == "template_def":
-                        #     print(get_text(self.src, q[0].start_byte, q[0].end_byte).decode())
                         # The main capture the patch is looking for.
                         captures_bundle.append([q])
                     else:

suite/auto-sync/src/autosync/cpptranslator/Tests/test_patches.py

@@ -78,6 +78,7 @@
 from autosync.cpptranslator.patches.UseMarkup import UseMarkup
 from autosync.cpptranslator.patches.UsingDeclaration import UsingDeclaration
 from autosync.cpptranslator.TemplateCollector import TemplateCollector
+from autosync.cpptranslator.BadConditionCode import BadConditionCode
 from autosync.Helper import get_path
 from autosync.cpptranslator.patches.isUInt import IsUInt
 
@@ -295,6 +296,13 @@ def test_fieldfrominstr(self):
             syntax,
             b"fieldFromInstruction_4(Val, 0, 4)",
         )
+
+        syntax = b"static unsigned function(unsigned Insn) { return fieldFromInstruction(Insn, 6, 6); }"
+        self.check_patching_result(
+            patch,
+            syntax,
+            b"fieldFromInstruction_4(Insn, 6, 6)",
+        ) 
 
     def test_getnumoperands(self):
         patch = GetNumOperands(0)
@@ -612,3 +620,8 @@ def test_isuintn(self):
         patch = IsUInt(0)
         syntax = b"isUInt<RegUnitBits>(FirstRU);"
         self.check_patching_result(patch, syntax, b"isUIntN(RegUnitBits, FirstRU)")
+
+    def test_badconditioncode(self):
+        patch = BadConditionCode(0)
+        syntax = b"return BadConditionCode(BRCC)"
+        self.check_patching_result(patch, syntax, b"CS_ASSERT(0 && \"Unknown condition code passed\");")

suite/auto-sync/src/autosync/cpptranslator/patches/BadConditionCode.py

@@ -29,4 +29,4 @@ def get_main_capture_name(self) -> str:
         return "bad_condition_code"
 
     def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
-        return b'assert(0 && "Unknown condition code passed");'
+        return b"CS_ASSERT(0 && \"Unknown condition code passed\");"

suite/cstest/include/test_detail_arc.h

@@ -1,4 +1,4 @@
-// Copyright © 2024 Rot127 <[email protected]>
+// Copyright © 2024 Sibirtsev Dmitry <[email protected]>
 // SPDX-License-Identifier: BSD-3
 
 #ifndef TEST_DETAIL_ARC_H

suite/cstest/src/test_detail_arc.c

@@ -1,4 +1,4 @@
-// Copyright © 2024 Rot127 <[email protected]>
+// Copyright © 2024 Sibirtsev Dmitry <[email protected]>
 // SPDX-License-Identifier: BSD-3
 
 #include "test_compare.h"

suite/test_corpus3.py

@@ -136,7 +136,6 @@ def test_file(fname):
         ("CS_ARCH_HPPA", "CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN"): 57,
         ("CS_ARCH_HPPA", "CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN"): 58,
         ("CS_ARCH_ARC", "CS_MODE_LITTLE_ENDIAN"): 59,
-        ("CS_ARCH_ARC", "CS_MODE_BIG_ENDIAN"): 60,
     }
 
     # if not option in ('', 'None'):

tests/details/arc.yaml

@@ -1,7 +1,7 @@
 test_cases:
   -
     input:
-      bytes: [ 0x04, 0x11, 0x00, 0x00, 0x04, 0x11, 0x00, 0x02, 0x04, 0x11, 0x00, 0x04, 0x04, 0x11, 0x00, 0x01, 0x04, 0x11, 0x00, 0x03, 0x04, 0x11, 0x00, 0x05, 0x04, 0x11, 0x80, 0x00, 0x04, 0x11, 0x80, 0x02, 0x04, 0x11, 0x80, 0x04  ]
+      bytes: [ 0x04, 0x11, 0x00, 0x00, 0x04, 0x11, 0x00, 0x02, 0x04, 0x11, 0x00, 0x04, 0x04, 0x11, 0x00, 0x01, 0x04, 0x11, 0x00, 0x03, 0x04, 0x11, 0x00, 0x05, 0x04, 0x11, 0x80, 0x00, 0x04, 0x11, 0x80, 0x02, 0x04, 0x11, 0x80, 0x04, 0x2d, 0x0a, 0x40, 0x00, 0xca, 0x22, 0x81, 0x01 ]
       arch: "arc"
       options: [ CS_OPT_DETAIL, CS_MODE_LITTLE_ENDIAN ]
       address: 0x0
@@ -24,7 +24,6 @@ test_cases:
                 type: ARC_OP_IMM
                 imm: 4
                 access: CS_AC_READ
-
       -
         asm_text: "ld.aw %r0, [%r1,4]"
         details:
@@ -160,4 +159,46 @@ test_cases:
               -
                 type: ARC_OP_IMM
                 imm: 4
-                access: CS_AC_READ
+                access: CS_AC_READ
+      -
+        asm_text: "breq %r2, %r1, 80"
+        details:
+          arc:
+            operands:
+              -
+                type: ARC_OP_IMM
+                imm: 0
+                access: CS_AC_READ
+              -
+                type: ARC_OP_REG
+                reg: "%r2"
+                access: CS_AC_READ
+              -
+                type: ARC_OP_REG
+                reg: "%r1"
+                access: CS_AC_READ
+              -
+                type: ARC_OP_IMM
+                imm: 0x50
+                access: CS_AC_READ
+          regs_read: [ "%r2", "%r1" ]
+          groups: [ jump, branch_relative ]
+      -
+        asm_text: "mov.eq %r2, %r6"
+        details:
+          arc:
+            operands:
+              -
+                type: ARC_OP_IMM
+                imm: 1
+                access: CS_AC_READ
+              -
+                type: ARC_OP_REG
+                reg: "%r2"
+                access: CS_AC_WRITE
+              -
+                type: ARC_OP_REG
+                reg: "%r6"
+                access: CS_AC_READ
+          regs_read: [ "status32", "%r6" ]
+          regs_write: [ "%r2" ]