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Rot127 committed Mar 25, 2024
1 parent 5051f53 commit 1d9458d
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Showing 10 changed files with 2,006 additions and 1,589 deletions.
94 changes: 46 additions & 48 deletions arch/AArch64/AArch64AddressingModes.h
Original file line number Diff line number Diff line change
Expand Up @@ -59,7 +59,7 @@ typedef enum {
AArch64_AM_SXTH,
AArch64_AM_SXTW,
AArch64_AM_SXTX,
} AArch64_AM_ShiftExtendType ;
} AArch64_AM_ShiftExtendType;

/// getShiftName - Get the string encoding for the shift type.
static inline const char *
Expand Down Expand Up @@ -133,9 +133,8 @@ static inline unsigned AArch64_AM_getShiftValue(unsigned Imm)
/// {8-6} = shifter
/// {5-0} = imm
static inline unsigned AArch64_AM_getShifterImm(AArch64_AM_ShiftExtendType ST,
unsigned Imm)
unsigned Imm)
{

unsigned STEnc = 0;
switch (ST) {
default:
Expand Down Expand Up @@ -171,7 +170,6 @@ static inline unsigned AArch64_AM_getArithShiftValue(unsigned Imm)
/// getExtendType - Extract the extend type for operands of arithmetic ops.
static inline AArch64_AM_ShiftExtendType AArch64_AM_getExtendType(unsigned Imm)
{

switch (Imm) {
default:
assert(0 && "Compiler bug!");
Expand Down Expand Up @@ -209,7 +207,8 @@ AArch64_AM_getArithExtendType(unsigned Imm)
/// 101 ==> sxth
/// 110 ==> sxtw
/// 111 ==> sxtx
static inline unsigned AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType ET)
static inline unsigned
AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType ET)
{
switch (ET) {
default:
Expand Down Expand Up @@ -249,7 +248,6 @@ static inline unsigned AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType E
static inline unsigned
AArch64_AM_getArithExtendImm(AArch64_AM_ShiftExtendType ET, unsigned Imm)
{

return (AArch64_AM_getExtendEncoding(ET) << 3) | (Imm & 0x7);
}

Expand Down Expand Up @@ -281,7 +279,7 @@ AArch64_AM_getMemExtendType(unsigned Imm)
/// {3-1} = shifter
/// {0} = doshift
static inline unsigned AArch64_AM_getMemExtendImm(AArch64_AM_ShiftExtendType ET,
bool DoShift)
bool DoShift)
{
return (AArch64_AM_getExtendEncoding(ET) << 1) | (unsigned)DoShift;
}
Expand All @@ -296,12 +294,12 @@ static inline uint64_t AArch64_AM_ror(uint64_t elt, unsigned size)
/// size. If so, return true with "encoding" set to the encoded value in
/// the form N:immr:imms.
static inline bool AArch64_AM_processLogicalImmediate(uint64_t Imm,
unsigned RegSize,
uint64_t *Encoding)
unsigned RegSize,
uint64_t *Encoding)
{
if (Imm == 0ULL || Imm == ~0ULL ||
(RegSize != 64 &&
(Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize)))))
(RegSize != 64 &&
(Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize)))))
return false;

// First, determine the element size.
Expand Down Expand Up @@ -368,7 +366,7 @@ static inline bool AArch64_AM_isLogicalImmediate(uint64_t imm, unsigned regSize)
/// encodeLogicalImmediate - Return the encoded immediate value for a logical
/// immediate instruction of the given register size.
static inline uint64_t AArch64_AM_encodeLogicalImmediate(uint64_t imm,
unsigned regSize)
unsigned regSize)
{
uint64_t encoding = 0;
bool res = AArch64_AM_processLogicalImmediate(imm, regSize, &encoding);
Expand All @@ -381,7 +379,7 @@ static inline uint64_t AArch64_AM_encodeLogicalImmediate(uint64_t imm,
/// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
/// integer value it represents with regSize bits.
static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val,
unsigned regSize)
unsigned regSize)
{
// Extract the N, imms, and immr fields.
unsigned N = (val >> 12) & 1;
Expand Down Expand Up @@ -410,7 +408,7 @@ static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val,
/// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
/// is a valid encoding for an integer value with regSize bits.
static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val,
unsigned regSize)
unsigned regSize)
{
// Extract the N and imms fields needed for checking.
unsigned N = (val >> 12) & 1;
Expand All @@ -419,7 +417,7 @@ static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val,
if (regSize == 32 && N != 0) // undefined logical immediate encoding
return false;
int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
if (len < 0) // undefined logical immediate encoding
if (len < 0) // undefined logical immediate encoding
return false;
unsigned size = (1 << len);
unsigned S = imms & (size - 1);
Expand Down Expand Up @@ -461,7 +459,7 @@ static inline float AArch64_AM_getFPImmFloat(unsigned Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType1(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm & 0xffffff00ffffff00ULL) == 0);
((Imm & 0xffffff00ffffff00ULL) == 0);
}

static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType1(uint64_t Imm)
Expand All @@ -479,7 +477,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType1(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType2(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm & 0xffff00ffffff00ffULL) == 0);
((Imm & 0xffff00ffffff00ffULL) == 0);
}

static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType2(uint64_t Imm)
Expand All @@ -497,7 +495,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType2(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType3(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm & 0xff00ffffff00ffffULL) == 0);
((Imm & 0xff00ffffff00ffffULL) == 0);
}

static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType3(uint64_t Imm)
Expand All @@ -515,7 +513,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType3(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType4(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm & 0x00ffffff00ffffffULL) == 0);
((Imm & 0x00ffffff00ffffffULL) == 0);
}

static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType4(uint64_t Imm)
Expand All @@ -533,8 +531,8 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType4(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType5(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
(((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) &&
((Imm & 0xff00ff00ff00ff00ULL) == 0);
(((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) &&
((Imm & 0xff00ff00ff00ff00ULL) == 0);
}

static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType5(uint64_t Imm)
Expand All @@ -552,8 +550,8 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType5(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType6(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
(((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) &&
((Imm & 0x00ff00ff00ff00ffULL) == 0);
(((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) &&
((Imm & 0x00ff00ff00ff00ffULL) == 0);
}

static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType6(uint64_t Imm)
Expand All @@ -571,7 +569,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType6(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType7(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL);
((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL);
}

static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType7(uint64_t Imm)
Expand All @@ -589,7 +587,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType7(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType8(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL);
((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL);
}

static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType8(uint8_t Imm)
Expand All @@ -607,8 +605,8 @@ static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType8(uint64_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType9(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm >> 48) == (Imm & 0x0000ffffULL)) &&
((Imm >> 56) == (Imm & 0x000000ffULL));
((Imm >> 48) == (Imm & 0x0000ffffULL)) &&
((Imm >> 56) == (Imm & 0x000000ffULL));
}

static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType9(uint64_t Imm)
Expand Down Expand Up @@ -639,13 +637,13 @@ static inline bool AArch64_AM_isAdvSIMDModImmType10(uint64_t Imm)
uint64_t ByteH = Imm & 0x00000000000000ffULL;

return (ByteA == 0ULL || ByteA == 0xff00000000000000ULL) &&
(ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) &&
(ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) &&
(ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) &&
(ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) &&
(ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) &&
(ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) &&
(ByteH == 0ULL || ByteH == 0x00000000000000ffULL);
(ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) &&
(ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) &&
(ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) &&
(ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) &&
(ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) &&
(ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) &&
(ByteH == 0ULL || ByteH == 0x00000000000000ffULL);
}

static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType10(uint64_t Imm)
Expand Down Expand Up @@ -704,8 +702,8 @@ static inline bool AArch64_AM_isAdvSIMDModImmType11(uint64_t Imm)
{
uint64_t BString = (Imm & 0x7E000000ULL) >> 25;
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
(BString == 0x1f || BString == 0x20) &&
((Imm & 0x0007ffff0007ffffULL) == 0);
(BString == 0x1f || BString == 0x20) &&
((Imm & 0x0007ffff0007ffffULL) == 0);
}

static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType11(uint64_t Imm)
Expand Down Expand Up @@ -766,7 +764,7 @@ static inline bool AArch64_AM_isAdvSIMDModImmType12(uint64_t Imm)
{
uint64_t BString = (Imm & 0x7fc0000000000000ULL) >> 54;
return ((BString == 0xff || BString == 0x100) &&
((Imm & 0x0000ffffffffffffULL) == 0));
((Imm & 0x0000ffffffffffffULL) == 0));
}

static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType12(uint64_t Imm)
Expand Down Expand Up @@ -822,22 +820,22 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType12(uint8_t Imm)
return (EncVal << 32) | EncVal;
}


/// Returns true if Imm is the concatenation of a repeating pattern of type T.
#define DEFINE_isSVEMaskOfIdenticalElements(T) \
static inline bool CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, T)(int64_t Imm) \
{ \
#define DEFINE_isSVEMaskOfIdenticalElements(T) \
static inline bool CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, \
T)(int64_t Imm) \
{ \
union { \
int64_t In; \
T Out[sizeof(int64_t) / sizeof(T)]; \
} U_Parts; \
U_Parts.In = Imm; \
T *Parts = U_Parts.Out; \
for (int i = 0; i < (sizeof(int64_t) / sizeof(T)); i++) { \
for (int i = 0; i < (sizeof(int64_t) / sizeof(T)); i++) { \
if (Parts[i] != Parts[0]) \
return false; \
} \
return true; \
return true; \
}
DEFINE_isSVEMaskOfIdenticalElements(int8_t);
DEFINE_isSVEMaskOfIdenticalElements(int16_t);
Expand Down Expand Up @@ -907,13 +905,13 @@ AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm)
int8_t *B = U_B.Out;

if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int32_t)(Imm) &&
isSVECpyImm32(S[0]))
isSVECpyImm32(S[0]))
return false;
if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int16_t)(Imm) &&
isSVECpyImm16(H[0]))
isSVECpyImm16(H[0]))
return false;
if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int8_t)(Imm) &&
isSVECpyImm8(B[0]))
isSVECpyImm8(B[0]))
return false;
return AArch64_AM_isLogicalImmediate(Imm, 64);
}
Expand All @@ -928,7 +926,7 @@ inline static bool AArch64_AM_isAnyMOVZMovAlias(uint64_t Value, int RegWidth)
}

inline static bool AArch64_AM_isMOVZMovAlias(uint64_t Value, int Shift,
int RegWidth)
int RegWidth)
{
if (RegWidth == 32)
Value &= 0xffffffffULL;
Expand All @@ -941,7 +939,7 @@ inline static bool AArch64_AM_isMOVZMovAlias(uint64_t Value, int Shift,
}

inline static bool AArch64_AM_isMOVNMovAlias(uint64_t Value, int Shift,
int RegWidth)
int RegWidth)
{
// MOVZ takes precedence over MOVN.
if (AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth))
Expand Down
8 changes: 5 additions & 3 deletions arch/AArch64/AArch64BaseInfo.c
Original file line number Diff line number Diff line change
Expand Up @@ -126,14 +126,16 @@ static void utostr(uint64_t X, bool isNeg, char *result)
char *BufPtr = Buffer + 21;

Buffer[21] = '\0';
if (X == 0) *--BufPtr = '0'; // Handle special case...
if (X == 0)
*--BufPtr = '0'; // Handle special case...

while (X) {
*--BufPtr = X % 10 + '0';
X /= 10;
}

if (isNeg) *--BufPtr = '-'; // Add negative sign...
if (isNeg)
*--BufPtr = '-'; // Add negative sign...

// suppose that result is big enough
strncpy(result, BufPtr, sizeof(Buffer));
Expand All @@ -158,7 +160,7 @@ void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result)
utostr(CRm, false, CRmStr);

dummy = cs_snprintf(result, AARCH64_GRS_LEN, "s%s_%s_c%s_c%s_%s",
Op0Str, Op1Str, CRnStr, CRmStr, Op2Str);
Op0Str, Op1Str, CRnStr, CRmStr, Op2Str);
(void)dummy;
}

Expand Down
6 changes: 3 additions & 3 deletions arch/AArch64/AArch64BaseInfo.h
Original file line number Diff line number Diff line change
Expand Up @@ -707,7 +707,8 @@ typedef struct SysReg {
#include "AArch64GenSystemOperands.inc"

const AArch64SysReg_SysReg *AArch64SysReg_lookupSysRegByName(const char *Name);
const AArch64SysReg_SysReg *AArch64SysReg_lookupSysRegByEncoding(uint16_t Encoding);
const AArch64SysReg_SysReg *
AArch64SysReg_lookupSysRegByEncoding(uint16_t Encoding);
#define AARCH64_GRS_LEN 128
void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result);

Expand Down Expand Up @@ -855,8 +856,7 @@ inline static const char *AArch64PACKeyIDToString(AArch64PACKey_ID KeyID)
}

/// Return numeric key ID for 2-letter identifier string.
inline static AArch64PACKey_ID
AArch64StringToPACKeyID(const char *Name)
inline static AArch64PACKey_ID AArch64StringToPACKeyID(const char *Name)
{
if (strcmp(Name, "ia") == 0)
return AArch64PACKey_IA;
Expand Down
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