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Add IP and SP writes for ret
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@hainest
hainest committed Dec 10, 2024
1 parent ae50e0f commit b1ef9a2
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Showing 3 changed files with 24 additions and 43 deletions.
19 changes: 0 additions & 19 deletions arch/X86/X86Mapping.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1153,25 +1153,6 @@ void X86_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
break;
}
break;

case X86_INS_RET:
switch(h->mode) {
case CS_MODE_16:
insn->detail->regs_write[0] = X86_REG_SP;
insn->detail->regs_read[0] = X86_REG_SP;
break;
case CS_MODE_32:
insn->detail->regs_write[0] = X86_REG_ESP;
insn->detail->regs_read[0] = X86_REG_ESP;
break;
default: // 64-bit
insn->detail->regs_write[0] = X86_REG_RSP;
insn->detail->regs_read[0] = X86_REG_RSP;
break;
}
insn->detail->regs_write_count = 1;
insn->detail->regs_read_count = 1;
break;
}

memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
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24 changes: 12 additions & 12 deletions arch/X86/X86MappingInsn.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -7958,42 +7958,42 @@
{
X86_LRETIL, X86_INS_RETF, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0
{ 0 }, { X86_REG_SP, X86_REG_IP, X86_REG_CS, 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},

{
X86_LRETIQ, X86_INS_RETFQ, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0
{ 0 }, { X86_REG_RSP, X86_REG_RIP, X86_REG_CS, 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0
#endif
},

{
X86_LRETIW, X86_INS_RETF, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0
{ 0 }, { X86_REG_ESP, X86_REG_EIP, X86_REG_CS, 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},

{
X86_LRETL, X86_INS_RETF, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0
{ 0 }, { X86_REG_SP, X86_REG_IP, X86_REG_CS, 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},

{
X86_LRETQ, X86_INS_RETFQ, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0
{ 0 }, { X86_REG_RSP, X86_REG_RIP, X86_REG_CS, 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0
#endif
},

{
X86_LRETW, X86_INS_RETF, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0
{ 0 }, { X86_REG_ESP, X86_REG_EIP, X86_REG_CS, 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0
#endif
},

Expand Down Expand Up @@ -15378,42 +15378,42 @@
{
X86_RETIL, X86_INS_RET, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0
{ 0 }, { X86_REG_SP, X86_REG_IP, 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},

{
X86_RETIQ, X86_INS_RET, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0
{ 0 }, { X86_REG_RSP, X86_REG_RIP, 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0
#endif
},

{
X86_RETIW, X86_INS_RET, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0
{ 0 }, { X86_REG_ESP, X86_REG_EIP, 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},

{
X86_RETL, X86_INS_RET, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0
{ 0 }, { X86_REG_SP, X86_REG_IP, 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},

{
X86_RETQ, X86_INS_RET, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0
{ 0 }, { X86_REG_RSP, X86_REG_RIP, 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0
#endif
},

{
X86_RETW, X86_INS_RET, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0
{ 0 }, { X86_REG_ESP, X86_REG_EIP, 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},

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24 changes: 12 additions & 12 deletions arch/X86/X86MappingInsn_reduce.inc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4493,42 +4493,42 @@
{
X86_LRETIL, X86_INS_RETF, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0
{ 0 }, { X86_REG_SP, X86_REG_IP, X86_REG_CS, 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},

{
X86_LRETIQ, X86_INS_RETFQ, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0
{ 0 }, { X86_REG_RSP, X86_REG_RIP, X86_REG_CS, 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0
#endif
},

{
X86_LRETIW, X86_INS_RETF, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0
{ 0 }, { X86_REG_ESP, X86_REG_EIP, X86_REG_CS, 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},

{
X86_LRETL, X86_INS_RETF, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0
{ 0 }, { X86_REG_SP, X86_REG_IP, X86_REG_CS, 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},

{
X86_LRETQ, X86_INS_RETFQ, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0
{ 0 }, { X86_REG_RSP, X86_REG_RIP, X86_REG_CS, 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0
#endif
},

{
X86_LRETW, X86_INS_RETF, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0
{ 0 }, { X86_REG_ESP, X86_REG_EIP, X86_REG_CS, 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0
#endif
},

Expand Down Expand Up @@ -7251,42 +7251,42 @@
{
X86_RETIL, X86_INS_RET, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0
{ 0 }, { X86_REG_SP, X86_REG_IP, 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},

{
X86_RETIQ, X86_INS_RET, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0
{ 0 }, { X86_REG_RSP, X86_REG_RIP, 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0
#endif
},

{
X86_RETIW, X86_INS_RET, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0
{ 0 }, { X86_REG_ESP, X86_REG_EIP, 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},

{
X86_RETL, X86_INS_RET, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0
{ 0 }, { X86_REG_SP, X86_REG_IP, 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},

{
X86_RETQ, X86_INS_RET, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0
{ 0 }, { X86_REG_RSP, X86_REG_RIP, 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0
#endif
},

{
X86_RETW, X86_INS_RET, 0,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0
{ 0 }, { X86_REG_ESP, X86_REG_EIP, 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},

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