Update inc files and insn names

capstone-engine · Jan 5, 2025 · e2fa94f · e2fa94f
1 parent 43da7fa
commit e2fa94f
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Showing 10 changed files with 206 additions and 266 deletions.
diff --git a/arch/ARC/ARCDisassembler.c b/arch/ARC/ARCDisassembler.c
@@ -424,7 +424,7 @@ static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t
 			uint64_t Insn64;
 			if (!readInstruction64(Bytes, BytesLen, Address, Size, &Insn64))
 				return MCDisassembler_Fail;
-			Result = decodeInstruction(DecoderTable64, Instr,
+			Result = decodeInstruction_8(DecoderTable64, Instr,
 						   Insn64, Address, NULL);
 			if (MCDisassembler_Success == Result) {
 				;
@@ -444,7 +444,7 @@ static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t
 			uint64_t Insn48;
 			if (!readInstruction48(Bytes, BytesLen, Address, Size, &Insn48))
 				return MCDisassembler_Fail;
-			Result = decodeInstruction(DecoderTable48, Instr,
+			Result = decodeInstruction_8(DecoderTable48, Instr,
 						   Insn48, Address, NULL);
 			if (MCDisassembler_Success == Result) {
 				;

diff --git a/arch/ARC/ARCGenAsmWriter.inc b/arch/ARC/ARCGenAsmWriter.inc
@@ -12,7 +12,7 @@
 /* https://github.com/capstone-engine/llvm-capstone */
 
 #include <capstone/platform.h>
-#include <assert.h>
+#include "../../cs_priv.h"
 
 /// getMnemonic - This method is automatically generated by tablegen
 /// from the instruction set description.
@@ -1001,11 +1001,11 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
   SStream_concat0(O, MnemonicInfo.first);
 
   uint32_t Bits = MnemonicInfo.second;
-  assert(Bits != 0 && "Cannot print this instruction.");
+  CS_ASSERT_RET(Bits != 0 && "Cannot print this instruction.");
 
   // Fragment 0 encoded into 4 bits for 10 unique commands.
   switch ((Bits >> 11) & 15) {
-  default: assert(0 && "Invalid command number.");
+  default: CS_ASSERT_RET(0 && "Invalid command number.");
   case 0:
     // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
     return;
@@ -1074,7 +1074,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
 
   // Fragment 1 encoded into 4 bits for 10 unique commands.
   switch ((Bits >> 15) & 15) {
-  default: assert(0 && "Invalid command number.");
+  default: CS_ASSERT_RET(0 && "Invalid command number.");
   case 0:
     // ADJCALLSTACKDOWN, CTLZ, CTTZ, GETFI, STB_FAR, STH_FAR, ST_FAR, ADC_f_r...
     SStream_concat0(O, ", ");
@@ -1135,7 +1135,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
 
   // Fragment 2 encoded into 3 bits for 6 unique commands.
   switch ((Bits >> 19) & 7) {
-  default: assert(0 && "Invalid command number.");
+  default: CS_ASSERT_RET(0 && "Invalid command number.");
   case 0:
     // ADJCALLSTACKDOWN, CTLZ, CTTZ, GETFI, ADC_f_rrlimm, ADC_f_rrr, ADC_f_rr...
     printOperand(MI, 1, O);
@@ -1173,7 +1173,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
 
   // Fragment 3 encoded into 2 bits for 3 unique commands.
   switch ((Bits >> 22) & 3) {
-  default: assert(0 && "Invalid command number.");
+  default: CS_ASSERT_RET(0 && "Invalid command number.");
   case 0:
     // ADJCALLSTACKDOWN, CTLZ, CTTZ, GETFI, STB_FAR, STH_FAR, ST_FAR, ADD_S_l...
     return;
@@ -1192,7 +1192,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
 
   // Fragment 4 encoded into 2 bits for 3 unique commands.
   switch ((Bits >> 24) & 3) {
-  default: assert(0 && "Invalid command number.");
+  default: CS_ASSERT_RET(0 && "Invalid command number.");
   case 0:
     // ADC_f_rrlimm, ADC_f_rrr, ADC_f_rrs12, ADC_f_rru6, ADC_rrlimm, ADC_rrr,...
     printOperand(MI, 2, O);
@@ -1228,7 +1228,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
 /// for the specified register.
 static const char *getRegisterName(unsigned RegNo) {
 #ifndef CAPSTONE_DIET
-  assert(RegNo && RegNo < 66 && "Invalid register number!");
+  CS_ASSERT_RET_VAL(RegNo && RegNo < 66 && "Invalid register number!", NULL);
 
   static const char AsmStrs[] = {
   /* 0 */ "%r10\0"
@@ -1305,8 +1305,8 @@ static const char *getRegisterName(unsigned RegNo) {
     213, 237, 261, 285, 25, 54, 97, 131, 78, 
   };
 
-  assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&
-          "Invalid alt name index for register!");
+  CS_ASSERT_RET_VAL(*(AsmStrs+RegAsmOffset[RegNo-1]) &&
+          "Invalid alt name index for register!", NULL);
   return AsmStrs+RegAsmOffset[RegNo-1];
 #else
   return NULL;

diff --git a/arch/ARC/ARCGenCSInsnEnum.inc b/arch/ARC/ARCGenCSInsnEnum.inc
@@ -12,32 +12,27 @@
 /* https://github.com/capstone-engine/llvm-capstone */
 
   ARC_INS_INVALID,
-  ARC_INS_HASH,
+  ARC_INS_h,
   ARC_INS_PBR,
   ARC_INS_ERROR_FLS,
   ARC_INS_ERROR_FFS,
   ARC_INS_PLDFI,
   ARC_INS_STB_FAR,
   ARC_INS_STH_FAR,
   ARC_INS_ST_FAR,
-  ARC_INS_ADC_,
-  ARC_INS_ADC_F,
   ARC_INS_ADC,
+  ARC_INS_ADC_F,
   ARC_INS_ADD_S,
-  ARC_INS_ADD_,
-  ARC_INS_ADD_F,
   ARC_INS_ADD,
-  ARC_INS_AND_,
-  ARC_INS_AND_F,
+  ARC_INS_ADD_F,
   ARC_INS_AND,
+  ARC_INS_AND_F,
   ARC_INS_ASL_S,
-  ARC_INS_ASL_,
-  ARC_INS_ASL_F,
   ARC_INS_ASL,
+  ARC_INS_ASL_F,
   ARC_INS_ASR_S,
-  ARC_INS_ASR_,
-  ARC_INS_ASR_F,
   ARC_INS_ASR,
+  ARC_INS_ASR_F,
   ARC_INS_BCLR_S,
   ARC_INS_BEQ_S,
   ARC_INS_BGE_S,
@@ -141,49 +136,37 @@
   ARC_INS_LD,
   ARC_INS_LEAVE_S,
   ARC_INS_LR,
-  ARC_INS_LSR_,
-  ARC_INS_LSR_F,
   ARC_INS_LSR,
-  ARC_INS_MAX_,
-  ARC_INS_MAX_F,
+  ARC_INS_LSR_F,
   ARC_INS_MAX,
-  ARC_INS_MIN_,
-  ARC_INS_MIN_F,
+  ARC_INS_MAX_F,
   ARC_INS_MIN,
+  ARC_INS_MIN_F,
   ARC_INS_MOV_S_NE,
-  ARC_INS_MOV_,
-  ARC_INS_MOV_F,
   ARC_INS_MOV,
-  ARC_INS_MPYMU_,
-  ARC_INS_MPYMU_F,
+  ARC_INS_MOV_F,
   ARC_INS_MPYMU,
-  ARC_INS_MPYM_,
-  ARC_INS_MPYM_F,
+  ARC_INS_MPYMU_F,
   ARC_INS_MPYM,
-  ARC_INS_MPY_,
-  ARC_INS_MPY_F,
+  ARC_INS_MPYM_F,
   ARC_INS_MPY,
+  ARC_INS_MPY_F,
   ARC_INS_NORMH_F,
   ARC_INS_NORMH,
   ARC_INS_NORM_F,
   ARC_INS_NORM,
-  ARC_INS_OR_,
-  ARC_INS_OR_F,
   ARC_INS_OR,
+  ARC_INS_OR_F,
   ARC_INS_POP_S,
   ARC_INS_PUSH_S,
-  ARC_INS_ROR_,
-  ARC_INS_ROR_F,
   ARC_INS_ROR,
-  ARC_INS_RSUB_,
-  ARC_INS_RSUB_F,
+  ARC_INS_ROR_F,
   ARC_INS_RSUB,
-  ARC_INS_SBC_,
-  ARC_INS_SBC_F,
+  ARC_INS_RSUB_F,
   ARC_INS_SBC,
-  ARC_INS_SETEQ_,
-  ARC_INS_SETEQ_F,
+  ARC_INS_SBC_F,
   ARC_INS_SETEQ,
+  ARC_INS_SETEQ_F,
   ARC_INS_SEXB_F,
   ARC_INS_SEXB,
   ARC_INS_SEXH_F,
@@ -209,18 +192,13 @@
   ARC_INS_ST_DI_AW,
   ARC_INS_ST_DI,
   ARC_INS_ST,
-  ARC_INS_SUB1_,
-  ARC_INS_SUB1_F,
   ARC_INS_SUB1,
-  ARC_INS_SUB2_,
-  ARC_INS_SUB2_F,
+  ARC_INS_SUB1_F,
   ARC_INS_SUB2,
-  ARC_INS_SUB3_,
-  ARC_INS_SUB3_F,
+  ARC_INS_SUB2_F,
   ARC_INS_SUB3,
-  ARC_INS_SUB_,
-  ARC_INS_SUB_F,
+  ARC_INS_SUB3_F,
   ARC_INS_SUB,
-  ARC_INS_XOR_,
-  ARC_INS_XOR_F,
+  ARC_INS_SUB_F,
   ARC_INS_XOR,
+  ARC_INS_XOR_F,